SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 83

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
General Configuration Block
Bit
23
22
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Description
TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT or PP/ACB1/FPCI. This bit is set to 1 at
power-on if the TFT_PRSNT strap (EBGA ball AK13 / TEPBGA ball P29) is pulled high.
Ball #
EBGA / TEPBGA
H2 / D10
H3 / A9
J4 / A10
T1 / B17
T3 / D17
T4 / C17
U1 / A18
U3 / B18
V1 / C18
V2 / C19
V3 / A20
W1 / B20
W2 / C20
W3 / D20
Y1 / A21
Y3 / B21
AA1 / C21
AA3 / D21
AB1 / A22
AB2 / D22
AJ13 / N31
AL12 / N30
AL16 / V30
Note:
RSVD (Reserved). Must be set equal to PMR[14] (LPCSEL). The LPC_ROM strap (EBGA ball E4 / TEPBGA ball D6) deter-
mines the power-on reset (POR) state of PMR[14] and PMR[22].
1. PMR[27] = 0 and FPCI_MON = 0
2. PMR[27] = 1 or FPCI_MON = 1
3. ACCESS.bus interface 1 is not available if PMR[23] = 1.
4. If FPCI_MON strap is enabled, the TFT_PRSNT strap should pulled low.
0: PP/ACB1/FPCI
Name
GPIO1
IOCS1#
GPIO20
DOCCS#
GPIO17
IOCS0#
BUSY/WAIT#
F_C/BE1#
PE
F_C/BE2#
SLCT
F_C/BE3#
PD7
F_AD7
ACK#
FPCICLK
PD4
F_AD4
PD5
F_AD5
PD6
F_AD6
SLIN#/ASTRB#
F_IRDY#
PD3
F_AD3
PD2
F_AD2
PD1
F_AD1
INIT#
SMI_O
PD0
F_AD0
ERR#
F_C/BE0#
STB#/WRITE#
F_FRAME#
AFD#/DSTRB#
INTR_O
AB1C
AB1D
GXCLK
TEST3
(Continued)
Add’l Dependencies
PMR[13] = 0
PMR[13] = 1
PMR[7] = 0
PMR[7] = 1
PMR[5] = 0
PMR[5] = 1
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
Note 1
Note 2
None
None
PMR[29] = 0
PMR[29] = 1
83
TFTDCK
TFTD1
TFTD7
1: TFT
Name
TFTD12
TFTD0
TFTD3
TFTD14
TFTD15
TFTD13
TFTDE
TFTD10
TFTD11
TFTD16
TFTD9
TFTD8
TFTD5
TFTD6
TFTD4
TFTD17
TFTD2
GPIO20
DOCCS#
GPIO1
IOCS1#
FP_VDD_ON
Add’l Dependencies
None
None
None
None
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
None
Note 1
PMR[7] = 0
PMR[7] = 1
PMR[13] = 0
PMR[13] = 1
None
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