SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 284

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Index 20h-23h
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR4 Mask Register (F5 Index 50h).
Index 24h-27h
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR5 Mask Register (F5 Index 54h).
Index 28h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
Index 40h-43h
To use F5BAR0, the mask register should be programmed first. The mask register defines the size of F5BAR0 and whether the
accessed offset registers are memory or I/O mapped.
Note:
Memory Base Address Register (Bit 0 = 0)
I/O Base Address Register (Bit 0 = 1)
Index 44h-47h
To use F5BAR1, the mask register should be programmed first. The mask register defines the size of F5BAR1 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note:
31:4
31:2
2:1
Bit
3
0
1
0
Whenever a value is written to this mask register, F5BAR0 must also be written (even if the value for F5BAR0 has not
changed).
Whenever a value is written to this mask register, F5BAR1 must also be written (even if the value for F5BAR1 has not
changed).
Description
Address Mask. Determines the size of the BAR.
Since the address mask goes down to bit 4, the smallest memory region is 16 bytes, however, the PCI specification sug-
gests not using less than a 4 KB address range.
Prefetchable . Indicates whether or not the data in memory is prefetchable. This bit should be set to 1 only if all the following
are true:
0: Data is not prefetchable. This value is recommended if one or more of the above listed conditions is not true.
1: Data is prefetchable.
Type.
00: Located anywhere in the 32-bit address space
01: Located below 1 MB
10: Located anywhere in the 64-bit address space
11: Reserved
This bit must be set to 0, to indicate memory base address register.
Address Mask. Determines the size of the BAR.
Since the address mask goes down to bit 2, the smallest I/O region is 4 bytes, however, the PCI Specification suggests not
using less than a 4 KB address range.
Reserved. Must be set to 0.
This bit must be set to 1, to indicate an I/O base address register.
— Every bit that is a 1 is programmable in the BAR.
— Every bit that is a 0 is fixed 0 in the BAR.
— There are no side-effects from reads (i.e., the data at the location is not changed as a result of the read).
— The device returns all bytes regardless of the byte enables.
— Host bridges can merge processor writes into this range without causing errors.
— The memory is not cached from the host processor.
— Every bit that is a 1 is programmable in the BAR.
— Every bit that is a 0 is fixed 0 in the BAR.
Table 5-39. F5: PCI Header Registers for X-Bus Expansion (Continued)
(Continued)
Base Address Register 4 - F5BAR4 (R/W)
Base Address Register 5 - F5BAR5 (R/W)
F5BAR0 Mask Address Register (R/W)
F5BAR1 Mask Address Register (R/W)
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reserved
Reserved
284
Reset Value: FFFFFFC1h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 100Bh
Reset Value: 0505h
Reset Value: 00h
Reset Value: 00h
Revision 3.0