SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 46

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Signal Definitions
Ball
No.
AK5
AK6
AK7
AK8
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
6, 2
6
6, 2
6
6
6
6
6
6
6
6
6
6
Signal Name
GPWIO1
PWRCNT1
V
IRRX1
SIN3
MD1
V
MD7
RASA#
V
BA1
MA2
V
MD35
MD46
V
MD43
DQM5
V
MA5
MD15
V
MD14
MD12
SDCLK_OUT
MD16
V
V
V
V
V
LED#
V
V
PWRCNT2
SDATA_IN2
MD2
MD4
SS
SS
IO
IO
IO
SS
SS
SS
IO
SS
IO
BAT
SB
SBL
Table 2-4.
(PU/PD)
(PU
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
100
(Continued)
)
481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
Buffer
TS
OD
TS
TS
TS
TS
TS
TS
TS
TS
TS
OD
OD
TS
TS
Type
IN
IN
IN
IN
O
O
O
O
O
O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
---
---
---
---
---
---
---
---
---
---
---
---
---
2/5
2/5
2/5
2/5
2/5
2/5
Ts
2/14
TS
TS
TS
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
T
T
T
T
T
T
T
T
T
T
T
14
14
14
,
,
,
,
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
---
---
---
---
SB
SB
SB
SB
SB
SB
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
---
---
---
PMR[6] = 0
PMR[6] =1
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
F3BAR0+Memory
Offset 08h[21] = 1
---
---
46
1.
2.
3.
4.
5.
6.
Ball
No.
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
6
6
6
6
6
6
6
6
For Buffer Type definitions, refer to Table 8-9 "Buffer Types" on page
364.
Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#,
PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#,
PWRCNT[2:1]).
The TFT_PRSNT strap determines the power-on reset (POR) state of
PMR[23].
The LPC_ROM strap determines the power-on reset (POR) state of
PMR[14] and PMR[22].
May need 5V tolerant protection at system level (DDC_SCL,
DDC_SDA).
Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1,
DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3,
ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE,
SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).
Signal Name
DQM0
CS0#
V
MA0
DQM4
V
MD38
MD39
V
MD44
MD40
CKEA
MA7
MA4
MD8
MD10
MD9
MA12
MD23
V
V
SS
SS
SS
IO
SS
(PU/PD)
GND
GND
GND
PWR
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
Buffer
TS
TS
TS
TS
TS
TS
TS
TS
Type
O
O
O
O
O
O
O
O
IN
IN
IN
IN
IN
IN
IN
IN
---
---
---
---
---
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
T
T
T
T
T
T
T
T
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
---
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Revision 3.0