SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 14

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Architecture Overview
GX_BASE+840Ch-840Fh
Note:
30:28
27:24
23:20
18:16
14:12
10:8
6:4
3:0
6:4
3:0
Bit
31
19
15
11
7
Refer to the SDRAM manufacturer’s specification for more information on component banks.
Description
SODIMM_PG_SZ (SODIMM Page Size - Banks 0 and 1). Selects the page size of SODIMM:
000: 1 KB
001: 2 KB
Both banks 0 and 1 must have the same page size.
RSVD (Reserved). Write as 0.
RSVD (Reserved). Write as 0.
LTMODE (CAS Latency). CAS latency is the delay, in SDRAM clock cycles, between the registration of a read command
and the availability of the first piece of output data. This parameter significantly affects system performance. Optimal setting
should be used. If an SODIMM is used, BIOS can interrogate EEPROM across the ACCESS.bus interface to determine this
value:
000: Reserved
001: Reserved
This field will not take effect until SDRAMPRG (bit 0 of MC_MEM_CNTRL1) transitions from 0 to 1.
RC (RFSH to RFSH/ACT Command Period, tRC). Minimum number of SDRAM clock between RFSH and RFSH/ACT
commands:
0000: Reserved
0001: 2 CLK
0010: 3 CLK
0011: 4 CLK
RAS (ACT to PRE Command Period, tRAS). Minimum number of SDRAM clocks between ACT and PRE commands:
0000: Reserved
0001: 2 CLK
0010: 3 CLK
0011: 4 CLK
RSVD (Reserved). Write as 0.
RP (PRE to ACT Command Period, tRP). Minimum number of SDRAM clocks between PRE and ACT commands:
000: Reserved
001: 1 CLK
RSVD (Reserved). Write as 0.
RCD (Delay Time ACT to READ/WRT Command, tRCD). Minimum number of SDRAM clock between ACT and
READ/WRT commands. This parameter significantly affects system performance. Optimal setting should be used:
000: Reserved
001: 1 CLK
RSVD (Reserved). Write as 0.
RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command
to two different component banks within the same module bank. The memory controller does not perform back-to-back Acti-
vate commands to two different component banks without a READ or WRITE command between them. Hence, this field
should be written as 001.
RSVD (Reserved). Write as 0.
DPL (Data-in to PRE command period, tDPL). Minimum number of SDRAM clocks from the time the last write datum is
sampled till the bank is precharged:
000: Reserved
001: 1 CLK
RSVD (Reserved). Leave unchanged. Always returns a 101h.
Table 1-2. SC2200 Memory Controller Registers (Continued)
010: 4 KB
011: 8 KB
010: 2 CLK
011: 3 CLK
0100: 5 CLK
0101: 6 CLK
0110: 7 CLK
0111: 8 CLK
0100: 5 CLK
0101: 6 CLK
0110: 7 CLK
0111: 8 CLK
010: 2 CLK
011: 3 CLK
010: 2 CLK
011: 3 CLK
010: 2 CLK
011: 3 CLK
(Continued)
1xx: 16 KB
111: SODIMM not installed
100: 4 CLK
101: 5 CLK
1000: 9 CLK
1001: 10 CLK
1010: 11 CLK
1011: 12 CLK
1000: 9 CLK
1001: 10 CLK
1010: 11 CLK
1011: 12 CLK
100: 4 CLK
101: 5 CLK
100: 4 CLK
101: 5 CLK
100: 4 CLK
101: 5 CLK
MC_SYNC_TIM1 (R/W)
14
110: 6 CLK
111: 7 CLK
1100: 13 CLK
1101: 14 CLK
1110: 15 CLK
1111: 16 CLK
1100: 13 CLK
1101: 14 CLK
1110: 15 CLK
1111: 16 CLK
110: 6 CLK
111: 7 CLK
110: 6 CLK
111: 7 CLK
110: 6 CLK
111: 7 CLK
Reset Value: 2A733225h
Revision 3.0