SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 202

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 40h
Index 41h
7:6
7:6
Bit
5
4
3
2
1
0
5
4
3
2
1
Description
Reserved. Must be set to 0.
Reserved. Must be set to 0.
PCI Subtractive Decode.
0: Disable transfer of subtractive decode address to external PCI bus. External PCI bus is not usable.
1: Enable transfer of subtractive decode address to external PCI bus. Recommended setting.
Reserved. Must be set to 1.
Reserved. Must be set to 0.
PERR# Signals SERR#. Assert SERR# when PERR# is asserted or detected as active by the Core Logic module (allows
PERR# assertion to be cascaded to NMI (SMI) generation in the system).
0: Disable.
1: Enable.
PCI Interrupt Acknowledge Cycle Response. The Core Logic module responds to PCI interrupt acknowledge cycles.
0: Disable.
1: Enable.
Reserved. Must be set to 0.
X-Bus Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 5
(F5) register space, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
Video Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 4
(F4) register space, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
XpressAUDIO Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI
Function 3 (F3) register space, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
IDE Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 2
(F2) register space, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
Power Management Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in
PCI Function 1 (F1) register space, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
(Continued)
PCI Function Control Register 1 (R/W)
PCI Function Control Register 2 (R/W)
202
Reset Value: 39h
Reset Value: 00h
Revision 3.0