SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 240

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Offset 14h-17h
Offset 18h-1Bh
31:23
22:19
18:15
13:12
11:10
31:16
15:9
9:8
7:5
4:2
1:0
8:0
Bit
14
Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Description
Reserved.
LPC Game Port 1 Address Select. Selects I/O Port:
0000: 200h
0001: 201h
0010: 202h
0011: 203h
Selected address range is enabled via F0BAR1+I/O Offset 10h[8].
LPC Game Port 0 Address Select. Selects I/O Port:
0000: 200h
0001: 201h
0010: 202h
0011: 203h
Selected address range is enabled via F0BAR1+I/O Offset 10h[7].
LPC Floppy Disk Controller Address Select. Selects I/O Port:
0: 3F0h-3F7h.
1: 370h-377h.
Selected address range is enabled via F0BAR1+I/O Offset 10h[6].
LPC Microsoft Sound System (MSS) Address Select. Selects I/O Port:
00: 530h-537h
01: 604h-60Bh
Selected address range is enabled via F0BAR1+I/O Offset 10h[5].
LPC MIDI Address Select. Selects I/O Port:
00: 300h-301h
01: 310h-311h
Selected address range is enabled via F0BAR1+I/O Offset 10h[4].
LPC Audio Address Select. Selects I/O Port:
00: 220h-233h
01: 240h-253h
Selected address range is enabled via F0BAR1+I/O Offset 10h[3].
LPC Serial Port 1 Address Select. Selects I/O Port:
000: 3F8h-3FFh
001: 2F8h-2FFh
Selected address range is enabled via F0BAR1+I/O Offset 10h[2].
LPC Serial Port 0 Address Select. Selects I/O Port:
000: 3F8h-3FFh
001: 2F8h-2FFh
Selected address range is enabled via F0BAR1+I/O Offset 10h[1].
LPC Parallel Port Address Select. Selects I/O Port:
00: 378h-37Fh (+778h-77Fh for ECP)
10: 3BCh-3BFh (+7BCh-7BFh for ECP)
Selected address range is enabled via F0BAR1+I/O Offset 10h[0].
Note:
Reserved. Must be set to 0.
Wide Generic Base Address Select. Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. AC97
and other configuration registers are expected to be mapped to this range. It is wide enough to allow many unforeseen
devices to be supported. Enabled at F0BAR1+I/O Offset 10h[9].
Note:
Reserved. Must be set to 0.
279h is read only, writes are forwarded to ISA for PnP.
The selected range must not overlap any address range that is positively decoded by F0BAR1+I/O Offset 10h bits
[17], [14:10], and [8:0].
(Continued)
LAD_D0 — LPC Address Decode 0 Register (R/W)
LAD_D1 — LPC Address Decode 1 Register (R/W)
0100: 204h
0101: 205h
0110: 206h
0111: 207h
0100: 204h
0101: 205h
0110: 206h
0111: 207h
10: E80h-E87h
11: F40h-F47h
10: 320h-321h
11: 330h-331h
10: 260h-273h
11: 280h-293h
010: 220h-227h
011: 228h-22Fh
010: 220h-227h
011: 228h-22Fh
240
1000: 208h
1001: 209h
1010: 20Ah
1011: 20Bh
1000: 208h
1001: 209h
1010: 20Ah
1011: 20Bh
100: 238h-23Fh
101: 2E8h-2EFh
100: 238h-23Fh
101: 2E8h-2EFh
01: 278h-27Fh (+678h-67Fh for ECP) (Note)
11: Reserved
1100: 20Ch
1101: 20Dh
1110: 20Eh
1111: 20Fh
1100: 20Ch
1101: 20Dh
1110: 20Eh
1111: 20Fh
110: 338h-33Fh
111: 3E8h-3EFh
110: 338h-33Fh
111: 3E8h-3EFh
Reset Value: 00080020h
Reset Value: 00000000h
Revision 3.0