SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 343

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Video Processor Module
Offset 20h-23h
Provides the video palette data. The data can be read or written to the Gamma Correction RAM (palette) via this register. Prior to
accessing this register, an appropriate address should be loaded to the Palette Address register (F4BAR0+Memory Offset 1Ch[7:0]).
Subsequent accesses to the Palette Data register cause the internal address counter to be incremented for the next cycle.
Offset 24h-27h
Offset 28h-2Bh
Configuration and control register for miscellaneous characteristics of the Video Processor.
Offset 2Ch-2Fh
Determines the characteristics of the integrated PLL2.
31:13
31:23
22:21
19:16
31:8
7:0
9:1
Bit
12
11
10
20
15
0
Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
PAL_DATA (Palette Data). Contains the read or write data for a Gamma Correction RAM (palette).
Note: When a read or write to the Gamma Correction RAM occurs, the previous output value is held for one additional DOT-
CLK period. This effect should go unnoticed during normal operation.
Reserved.
Reserved.
PLL2_PWR_EN (PLL2 Power-Down Enable).
0: Power-down.
1: Normal.
A_PWR_DN (Analog Power-Down). Enables power-down of the PLL2 and the bandgap circuit that generates VREF.
0: Normal.
1: Power-down.
Note:
DAC_PWR_DN (DAC Power-Down). Powers down the internal CRT DAC.
0: Normal.
1: Power-down.
Reserved.
GAMMA_EN (Gamma Correction RAM Enable). Allows video or graphics (selected by F0BAR0+Memory Offset 04h[21])
to go to the Gamma Correction RAM.
0: Enable.
1: Disable.
Reserved. Must be set to 0.
CLK_DIV_SEL (Clock Divider Select).
00: No division
01: Divide by 2
10: Divide by 4
11: Divide by 8
Divides the clock generated by the PLL2, using the programmed m (bits [14:8]) and n (bits [3:0]) values.
SEL_REG_CAL. Selects specific or previously-calculated values.
0: Values previously calculated from the CLK_SEL bits (bits [19:16]).
1: Values according to the m (bits [14:8]), n (bits [3:0]), and CLK_DIV_SEL (bits [22:21]) fields.
CLK_SEL (Clock Select). Selects frequency (in MHz) of the display clock.
0000: 25.175
0001: 31.5
0010: 36
0011: 40
LFTC (Loop Filter Time Constant). This bit should be set when m (bits [14:8]) value is higher than 30.
If A_PWR_DN is set to 1 without also setting DAC_PWR_DN (bit 10) to 1, an unexpected increase in power con-
sumption may result.
0100: 50
0101: 49.5
0110: 56.25
0111: 44.9
Palette (Gamma Correction RAM) Data Register (R/W)
(Continued)
PLL2 Clock Select Register (R/W)
Miscellaneous Register (R/W)
1000: 65
1001: 75
1010: 78.5
1011: 94.5
Reserved
343
1100: 108
1101: 135
1110: 27
1111: 24.923052
Reset Value: xxxxxxxxh
Reset Value: 00001400h
Reset Value: 00000000h
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