SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 138

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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SuperI/O Module
4.8
This section briefly describes the following blocks that pro-
vide legacy device functions:
• Parallel Port.
• Serial Port 1 and Serial Port 2 (SP1 and SP2), UART
• Infrared Communications Port / Serial Port 3 function-
Notes
• SP1 and SP2 are similar to SCC1 in the National
• The Parallel Port is similar to Parallel Port in the National
• The IR Communications Port is similar to SCC2 in the
functionality for both SP1 and SP2.
ality.
PC87338 device.
PC87338 device.
National PC87338 device.
Second Level Offset
First Level Offset
LEGACY FUNCTIONAL BLOCKS
000h
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h
00h
02h
04h
05h
Table 4-34. Parallel Port Register Map for Second Level Offset
(Continued)
Table 4-33. Parallel Port Register Map for First Level Offset
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
W
W
Name
DATAR. PP Data
AFIFO. ECP Address FIFO
DSR. Status
DCR. Control
ADDR. EPP Address
DATA0. EPP Data Port 0
DATA1. EPP Data Port 1
DATA2. EPP Data Port 2
DATA3. EPP Data Port 3
CFIFO. PP Data FIFO
DFIFO. ECP Data FIFO
TFIFO. Test FIFO
CNFGA. Configuration A
CNFGB. Configuration B
ECR. Extended Control
EIR. Extended Index
EDR. Extended Data
EAR. Extended Auxiliary Status
Name
Control0. Control Register 0
Control2. Control Register 2
Control4. Control Register 4
PP Confg0. Parallel Port Configuration Register 0
138
The description of each Legacy block includes a general
description, register maps, and bit maps. For more informa-
tion about legacy blocks, contact your National Semicon-
ductor representative.
4.8.1
The Parallel Port supports all IEEE1284 standard commu-
nication modes: Compatibility (known also as Standard or
SPP), Bidirectional (known also as PS/2), FIFO, EPP
(known also as Mode 4) and ECP (with an optional
Extended ECP mode).
4.8.1.1
The Parallel Port register maps (Table 4-33 and Table 4-34)
are grouped according to first and second level offsets.
EPP and second level offset registers are available only
when the base address is 8-byte aligned.
Parallel Port functional block bit maps are shown in Table 4-
35 and Table 4-36.
Parallel Port
Parallel Port Register and Bit Maps
Modes (ECR Bits) 7 6 5
000 or 001
All Modes
All Modes
All Modes
All Modes
All Modes
All Modes
011
100
100
100
100
100
010
011
110
111
111
Revision 3.0