SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 81

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
General Configuration Block
3.2
The registers described inTable 3-2 are used to determine
general configuration for the SC2200. These registers also
indicate which multiplexed signals are issued via balls from
Offset 30h-33h
This register configures pins with multiple functions. See Section 2.1 on page 20 for more information about multiplexing information.
31:30
Bit
29
28
27
26
MULTIPLEXING, INTERRUPT SELECTION, AND BASE ADDRESS REGISTERS
Description
Reserved: Always write 0.
Test Signals. Selects ball functions.
Ball #
EBGA / TEPBGA
D28 / AH3
C28 / AG4
B29 / AJ1
AL16 / V30
Test Signals. Selects ball function.
Ball #
EBGA / TEPBGA
AJ4 / E28
Note:
FPCI_MON (Fast-PCI Monitoring). Selects Fast-PCI monitoring output signals instead of Parallel Port signals.
Fast-PCI monitoring output signals can be enabled in two ways: by setting this bit to 1 or by strapping FPCI_MON (EBGA
ball D3 / TEPBGA ball A4) high. (The strapped value can be read back at MCR[30].) Listed below is how these two options
work together and the signals that are enabled (enabling overrides add’l dependencies except FPCI_MON = 1). Note that
the FPCI monitoring signals that are muxed with Audio signals are not enabled via this bit. They are only enabled using the
strap option.
Ball #
EBGA / TEPBGA
U3 / B18
U1 / A18
V3 / A20
V2 / C19
V1 / C18
W2 / C20
W3 / D20
Y1 / A21
AA1 / C21
T4 / C17
T3 / D17
T1 / B17
AA3 / D21
AB1 / A22
W1 / B20
AB2 / D22
Y3 / B21
AL15 / V31
AJ15 / U29
AK14 / U31
AL14 / U30
Note:
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers
If this bit is set, PMR[8] and PMR[18] must be set by software.
Reserved: Always write 0.
PMR[27] FPCI_MON
0
0
1
1
0: Internal Test Signals
Name
PLL2B
PLL6B
PLL5B
GXCLK
0: AC97 Signal
Name
SIN2
FPCI_MON Signal Other Signal
FPCICLK
F_AD7
F_AD6
F_AD5
F_AD4
F_AD3
F_AD2
F_AD1
F_AD0
F_C/BE3#
F_C/BE2#
F_C/BE1#
F_C/BE0#
F_FRAME#
F_IRDY#
INTR_O
SMI_O
F_DEVSEL#
F_STOP#
F_GNT0#
F_TRDY#
0
1
0
1
Pin Multiplexing Register - PMR (R/W)
(Continued)
Disable all Fast-PCI monitoring signals
Enable all Fast-PCI monitoring signals
Enable Fast-PCI monitoring signals muxed with Parallel Port signals only
Enable all Fast-PCI monitoring signals
Add’l Dependencies
None
None
None
See PMR[23]
Add’l Dependencies
None
ACK#+TFTDE
PD7+TFTD13
PD6+TFTD1
PD5+TFT11
PD4+TFTD10
PD3+TFTD9
PD2+TFTD8
PD1+TFTD7
PD0_TFTD5
SLCT+TFTD15
PE+TFTD14
BUSY/WAIT#+TFTD3
ERR#+TFTD4
STB#/WRITE#+TFTD7
SLIN#/ASTRB#+TFTD16
AFD#/DSTRB#+TFTD2
INIT#+TFTD5
GPIO16+PC_BEEP
AC97_RST#
SDATA_IN
BIT_CLK
81
which more than one signal may be output. For more infor-
mation about multiplexed signals and the appropriate con-
figurations, see Section 2.1 "Ball Assignments" on page 20.
1: Internal Test Signals
1: Internal Test Signal
Name
TEST0
TEST1
TEST2
TEST3
Name
SDTEST3
Add’l Dependencies
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
FPCI_MON = 1 and see PMR[0]
FPCI_MON = 1
FPCI_MON = 1
FPCI_MON = 1
Add’l Dependencies
None
None
None
PMR[23] = 0
Add’l Dependencies
See Note.
Reset Value: 00000000h
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