SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 29

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
Ball
No.
AH8
AH9
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
4
4
4
4
4
4
4
Signal Name
VPD4
VPD0
V
V
V
V
V
V
SDCLK1
V
V
V
V
V
V
MD28
MD55
MD51
MD48
MD23
SDCLK_OUT
MA12
MD11
MD10
GPIO10
DSR2#
IDE_IORDY1
SDTEST1
GPIO8
CTS2#
IDE_DREQ1
SDTEST4
V
SIN2
SDTEST3
TMS
VPD7
SS
CORE
SS
CORE
SS
CORE
CORE
SS
CORE
SS
CORE
SS
IO
Table 2-2.
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
22.5
I
22.5
I
22.5
22.5
22.5
I
22.5
I
22.5
22.5
I
I
22.5
I
(Continued)
)
)
)
)
)
)
)
)
)
Buffer
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
TS
TS
TS
TS
TS
TS
TS
IN
IN
Type
IN
IN
IN
IN
IN
IN
O
O
O
O
O
O
O
O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
---
---
---
---
---
---
---
---
---
---
---
---
---
TS1
TS1
2/5
2/5
2/5
8/8
2/5
8/8
2/5
2/5
PCI
TS
TS
TS
TS
TS
2/5
2/5
2/5
2/5
2/5
2/5
2/5
T
T
T
T
T
T
T
T
T
T
,
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
PMR[17] = 0 and
PMR[8] = 0
PMR[17] = 1 and
PMR[8] = 0
PMR[17] = 0 and
PMR[8] = 1
PMR[17] = 1 and
PMR[8] = 1
---
PMR[28] = 0
PMR[28] = 1
---
---
29
Ball
No.
AJ7
AJ8
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
4
4
4
4
4
4
4
Signal Name
VPD6
VPD2
GPIO38/IRRX2
LPCPD#
GPIO35
LAD3
GPIO32
LAD0
GPIO12
AB2C
AB1C
GPIO20
DOCCS#
AC97_CLK
AC97_RST#
F_STOP#
SDCLK3
MD56
MD58
MD61
DQM7
DQM3
MD25
MD29
MD54
MD50
DQM6
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
)
)
)
)
)
)
)
)
)
Buffer
IN
IN
IN
IN
IN
IN
IN
IN
TS
TS
TS
TS
TS
TS
TS
Type
O3/5
O
O
O
O
O
O
O
OD
OD
O
O
O
O
O
O
O
O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
AB
8/8
AB
AB
3/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
T
T
T
T
T
T
T
T
T
T
8
8
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
---
---
PMR[14]
PMR[22]
IRRX2 input is con-
nected to the input
path of GPIO38.
There is no logic
required to enable
IRRX2, just a sim-
ple connection.
Hence, when
GPIO38 is the
selected function,
IRRX2 is also
selected.
PMR[14]
PMR[22]
PMR[14]
PMR[22]
PMR[14]
PMR[22]
PMR[14]
PMR[22]
PMR[14]
PMR[22]
PMR[19] = 0
PMR[19] = 1
PMR[23]
PMR[23]
PMR[7] = 0
PMR[23]
PMR[7] = 1
PMR[25] = 1
FPCI_MON = 0
FPCI_MON = 1
---
---
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---
---
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6
6
6
6
6
6
6
6
6
6
6
6
3
3
3
= 0 and
= 0. The
= 1 and
= 1
= 0 and
= 0
= 1 and
= 1
= 0 and
= 0
= 1 and
= 1
= 0
= 1 and
= 1 and