SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 243

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
5.4.2
The register space designated as Function 1 (F1) is used
to configure the PCI portion of support hardware for the
SMI Status and ACPI Support registers. The bit formats for
the PCI Header registers are given in Table 5-32.
Index 00h-01h
Index 02h-03h
Index 04h-05h
Index 06h-07h
Index 08h
Index 09h-0Bh
Index 0Ch
Index 0Dh
Index 0Eh
Index 0Fh
Index 10h-13h
This register allows access to I/O mapped SMI status related registers. Bits [7:0] are read only (0000 0001), indicating a 256-byte I/O
address range. Refer to Table 5-33 on page 244 for bit formats and reset values of the SMI status registers.
Index 14h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
Index 40h-43h
This register allows access to I/O mapped ACPI related registers. Bits [7:0] are read only (0000 0001), indicating a 256 byte address
range. Refer to Table 5-34 on page 253 for bit formats and reset values of the ACPI registers.
Note:
Index 44h-FFh
15:1
31:8
31:8
7:0
7:1
Bit
0
0
SMI Status and ACPI Registers - Function 1
This Base Address register moved from its normal PCI Header Space (F1 Index 14h) to prevent plug and play software from
relocating it after an FACP table is built.
Description
Reserved. (Read Only)
I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled to access I/O offsets through F1BAR0 and F1BAR1 (see F1 Index 10h and 40h).
SMI Status Base Address.
Address Range. (Read Only)
ACPI Base Address.
Address Range. (Read Only)
Enable. (Write Only) This bit must be set to 1 to enable access to ACPI Support Registers.
Table 5-32. F1: PCI Header Registers for SMI Status and ACPI Support
(Continued)
Base Address Register 0 - F1BAR0 (R/W)
Base Address Register 1 - F1BAR1 (R/W)
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Cache Line Size Register (RO)
Device Revision ID Register (RO)
PCI Latency Timer Register (RO)
PCI Class Code Register (RO)
PCI Command Register (R/W)
Subsystem Vendor ID (RO)
PCI Status Register (RO)
PCI BIST Register (RO)
PCI Header Type (RO)
Subsystem ID (RO)
Reserved
Reserved
Reserved
243
Located in the PCI Header registers of F1 are two Base
Address Registers (F1BARx) used for pointing to the regis-
ter spaces designated for SMI status and ACPI support,
described later in this section.
Reset Value: 00000001h
Reset Value: 00000001h
Reset Value: 068000h
Reset Value: 100Bh
Reset Value: 100Bh
Reset Value: 0501h
Reset Value: 0000h
Reset Value: 0280h
Reset Value: 0501h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
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