SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 126

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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SuperI/O Module
4.6.2
The SWC registers are organized in two banks. The offsets
are related to a base address that is determined by the
SWC Base Address Register in the logical device configu-
ration. The lower three registers are common to the two
banks while the upper registers (03h-0Fh) are divided as
follows:
Offset
Offset
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
SWC Registers
Table 4-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
Table 4-27. Banks 0 and 1 - Common Control and Status Register Map
R/W1C
Type
Type
(Continued)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
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WKSR. Wakeup Events Status Register
WKCR. Wakeup Events Control Register
WKCFG. Wakeup Configuration Register
Name
IRWCR. CEIR Wakeup Control Register
RSVD. Reserved
IRWAD. CEIR Wakeup Address Register
IRWAM. CEIR Wakeup Address Mask Register
ADSR. CEIR Address Shift Register
IRWTR0L. CEIR Wakeup, Range 0, Low Limit Register
IRWTR0H. CEIR Wakeup, Range 0, High Limit Register
IRWTR1L. CEIR Wakeup, Range 1, Low Limit Register
IRWTR1H. CEIR Wakeup, Range 1, High Limit Register
IRWTR2L. CEIR Wakeup, Range 2, Low Limit Register
IRWTR2H. CEIR Wakeup, Range 2, High Limit Register
IRWTR3L. CEIR Wakeup, Range 3, Low Limit Register
IRWTR3H. CEIR Wakeup, Range 3, High Limit Register
Name
126
• Bank 0 holds reserved registers.
• Bank 1 holds the CEIR Control Registers.
The active bank is selected through the Configuration Bank
Select field (bits [1:0]) in the Wakeup Configuration Regis-
ter (WKCFG). See Table 4-29 on page 127.
The tables that follow provide register maps and bit defini-
tions for Banks 0 and 1.
Reset
Reset
Value
Value
E0h
0Bh
00h
03h
00h
00h
00h
00h
10h
14h
07h
50h
64h
28h
32h
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Revision 3.0