SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 39

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
Ball
No.
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
6,2
6,2
6,2
6,2
Signal Name
AV
SLCT
TFTD15
F_C/BE3#
PD4
TFTD10
F_AD4
PD5
TFTD11
F_AD5
PD3
TFTD9
F_AD3
PD0
TFTD6
F_AD0
V
NC
NC
V
INTB#
AV
GPIO9
DCD2#
IDE_IOW1#
SDTEST2
IO
IO
SSPLL2
SSUSB
Table 2-4.
(PU/PD)
(PU
(PU
(PU
(PU
(PU
PWR
PWR
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
---
---
O
O
O
O
O
O
O
O
O
O
O
O
I
I
22.5
22.5
I
22.5
22.5
22.5
(Continued)
)
)
)
)
)
481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
Buffer
O
O
O
O
O
O
O
O
Type
IN
IN
IN
O
O
O
O
O
O
O
O
O
IN
IN
IN
IN
IN
14/14
14/14
14/14
14/14
14/14
14/14
14/14
14/14
---
---
---
---
---
---
1/4
1/4
1/4
1/4
1/4
1/4
PCI
1/4
1/4
2/5
TS
TS
T
T
T
T
T
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
---
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
Configuration
---
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
---
---
---
---
---
---
PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
39
Ball
No.
C29
C30
C31
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
Signal Name
V
GPIO7
RTS2#
IDE_DACK1#
SDTEST0
GPIO8
CTS2#
IDE_DREQ1
SDTEST4
AD21
A21
AD22
A22
AD20
A20
AD27
D3
AD31
D7
PCICLK1
LPC_ROM
V
FRAME#
IOR#
DOCR#
GPIO14
GPIO1
IOCS1#
TFTD12
TRDE#
GPIO0
V
IO
SS
CCCRT
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PD
PWR
GND
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
22.5
22.5
22.5
22.5
22.5
I
22.5
I
22.5
22.5
I
22.5
22.5
22.5
22.5
22.5
22.5
100
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
Buffer
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Type
IN
IN
IN
IN
IN
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IN
STRP
---
---
---
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
TS1
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
TS
1/4
1/4
1/4
2/5
TS
8/8
2/5
3/5
3/5
TS
3/5
3/5
3/5
1/4
3/5
TS
3/5
TS
T
,
,
,
,
,
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
---
PMR[17] = 0 and
PMR[8] = 0
PMR[17] = 1 and
PMR[8] = 0
PMR[17] = 0 and
PMR[8] = 1
PMR[17] = 1 and
PMR[8] = 1
PMR[17] = 0 and
PMR[8] = 0
PMR[17] = 1 and
PMR[8] = 0
PMR[17] = 0 and
PMR[8] = 1
PMR[17] = 1 and
PMR[8] = 1
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
---
Strap (See Table 2-
6 on page 51.)
---
---
PMR[21] = 0 and
PMR[2] = 0
PMR[21] = 0 and
PMR[2] = 1
PMR[21] = 1 and
PMR[2] = 1
PMR[23]
PMR[13] = 0
PMR[23]
PMR[13] = 1
PMR[23]
PMR[12] = 0
PMR[12] = 1
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3
3
3
= 0 and
= 0 and
= 1