SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 371

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Electrical Specifications
1.
2.
Symbol
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
9
10
11
Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.
Load = 50 pF, V
Use the Min/Max equations [value+(x * y)] to calculate the actual value.
x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.
Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the GX1 Processor Series Datasheet
for more information.
For example, for a 266 MHz SC2200 running a 88.7 MHz SDRAM clock, with a shift value of 3:
t
t
1
1
Min = -3.5 + (3 * (5 * 0.45)) = 3.25 ns
Max = -1.0 + (3 * (5 * 0.45)) = 5.75 ns
Parameter
Control Output
MA[12:0], BA[1.0] Output
MD[63.0] Output
MD[63.0] Read Data in Setup to SDCLK_IN
MD[63:0] Read Data Hold to SDCLK_IN
SDCLK[3:0], SDCLK_OUT cycle time
233 MHz
266 MHz
300 MHz
SDCLK[3:0], SDCLK_OUT fall/rise time between
(V
SDCLK_IN fall/rise time between (V
SDCLK[3:0], SDCLK_OUT high time
233 MHz
266 MHz
300 MHz
SDCLK[3:0], SDCLK_OUT low time
233 MHz
266 MHz
300 MHz
OLD
-V
CORE
OHD
= 1.8V@ 233/266 MHz, V
)
1,2
2
Table 8-11. Memory Controller Timing Parameters
Valid from SDCLK[3:0]
Valid from SDCLK[3:0]
(Continued)
2
Valid from SDCLK[3:0]
ILD
CORE
-V
IHD
= 2.0V@ 300 MHz, V
)
371
-3.0 + (x
-3.2 + (x
-2.2 + (x
IO
= 3.3V, @25
Min
1.3
2.0
8.3
7.3
4.0
3.0
2.5
4.0
2.5
2.5
10
*
*
*
y)
y)
y)
o
C.
0.1 + (x
0.1 + (x
0.7 + (x
Max
13.5
12.5
14
2
2
*
*
*
y)
y)
y)
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns