SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 113

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
SuperI/O Module
4.4.2.6
The Parallel Port supports all IEEE 1284 standard commu-
nication modes: Compatibility (known also as Standard or
SPP), Bidirectional (known also as PS/2), FIFO, EPP
(known also as Mode 4) and ECP (with an optional
Extended ECP mode).
The Parallel Port includes two groups of runtime registers,
as follows:
• A group of 21 registers at first level offset, sharing 14
Index F0h
This register is reset by hardware to F2h.
Index
entries. Three of these registers (at Offset 403h, 404h,
and 405h) are used only in the Extended ECP mode.
30h
60h
61h
70h
71h
74h
75h
F0h
7:5
3:2
Bit
4
1
0
LDN 07h - Parallel Port
Description
Reserved. Must be 11.
Extended Register Access.
0: Registers at base (address)+403h, base+404h and base+405h are not accessible (reads and writes are ignored).
1: Registers at base (address)+403h, base+404h and base+405h are accessible. This option supports run-time configura-
Reserved.
Power Mode Control. When the logical device is active:
0: Parallel port clock disabled. ECP modes and EPP timeout are not functional when the logical device is active. Registers
1: Parallel port clock enabled. All operation modes are functional when the logical device is active. (Default)
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disable. (Default)
1: Enable.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
tion within the Parallel Port address space.
are maintained.
Configuration Register or Action
Activate. See also bit 0 of the SIOCF1 register.
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b. Bit 2 (for A10)
should be 0b.
Base Address LSB register. Bits 1 and 0 (A1 and A0) are RO, 00b. For ECP Mode 4
(EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.
Interrupt Number.
Interrupt Type.
Bits [7:2] are RO.
Bit 1 is R/W.
Bit 0 is RO. It reflects the interrupt type dictated by the Parallel Port operation mode.
This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all
other modes.
DMA Channel Select.
Report no second DMA assignment.
Parallel Port Configuration register. (See Table 4-16.)
(Continued)
Table 4-16. Parallel Port Configuration Register
Table 4-15. Relevant Parallel Port Registers
Parallel Port Configuration Register (R/W)
113
• A group of four registers, used only in the Extended ECP
The desired mode is selected by the ECR runtime register
(Offset 402h). The selected mode determines which runt-
ime registers are used and which address bits are used for
the base address. (See Section 4.8.1 on page 138 for fur-
ther details regarding the runtime registers.)
Table 4-15 lists the configuration registers which affect the
Parallel Port. Only the last register (F0h) is described here
(Table 4-16). See Table 4-3 "Standard Configuration Regis-
ters" on page 104 for descriptions of the others.
mode, accessed by a second level offset.
Reset Value: F2h
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Reset
Value
F2h
00h
02h
78h
07h
02h
04h
04h