SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 57

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
2.4.1
2.4.2
Signal Name
DID1
DID0
POR#
X32I
X32O
X27I
X27O
CLK27M
PCIRST#
Signal Name
MD[63:0]
MA[12:0]
BA1
BA0
System Interface (Continued)
Memory Interface Signals
Table 2-3
Table 2-3
on page
on page
EBGA
EBGA
C30
D29
A29
D27
A23
See
See
P31
P30
J29
32.
32.
D2
D4
D1
(Continued)
Ball No.
Ball No.
TEPBGA
TEPBGA
Table 2-5
Table 2-5
on page
on page
AK14
AJ13
AH9
AG3
AH2
AA4
AJ2
AJ3
See
See
C6
C5
47.
47.
A6
Type
Type
I/O
I/O
I/O
O
O
O
O
I
I
I
Description
Device ID. Together, the straps on these sig-
nals define the system-level chip ID.
The value of DID1 can be read in the
MCR[29]. The value of DID0 can be read in
the MCR[31].
DID0 must have a pull-up resistor of 1.5 K
and DID1 must have a pull-down resistor of
1.5 K .
Power On Reset. POR# is the system reset
signal generated from the power supply to
indicate that the system should be reset.
Crystal Connections. Connected directly to
a 32.768 KHz crystal. This clock input is
required even if the internal RTC is not being
used. Some of the internal clocks are derived
from this clock. If an external clock is used, it
should be connected to X32I, using a voltage
level of 0 volts to V
X32O should remain unconnected.
Crystal Connections. Connected directly to
a 27.000 MHz crystal. Some of the internal
clocks are derived from this clock. If an exter-
nal clock is used, it should be connected to
X27I, using a voltage level of 0 volts to V
and X27O should be remain unconnected.
27 MHz Output Clock. Output of crystal
oscillator.
PCI and System Reset. PCIRST# is the
reset signal for the PCI bus and system. It is
asserted for approximately 100 µs after
POR# is negated.
Description
Memory Data Bus. The data bus lines
driven to/from system memory.
Memory Address Bus. The multiplexed
row/column address lines driven to the sys-
tem memory. Supports 256-Mbit SDRAM.
Bank Address Bits. These bits are used to
select the component bank within the
SDRAM.
57
CORE
+10% maximum.
IO
IDE_DATA5
GNT1#
GNT0#
www.national.com
Mux
Mux
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