SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 233

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Offset 20h-23h
Offset 24h-27h
This register is used to indicate configuration for the GPIO signal that is selected in the GPIO Signal Configuration Select Register
(above).
Note:
31:6
31:7
Bit
5:0
6
5
PME debouncing, polarity, and edge/level configuration is only applicable on GPIO0-GPIO15 signals (Bank 0 = 00000 to
01111) and on GPIO32-GPIO47 signals (Bank 1 settings of 00000 to 01111). The remaining GPIOs (GPIO16-GPIO31 and
GPIO48-GPIO63) can not generate PMEs, therefore these bits have no function and read 0.
Description
Reserved. Must be set to 0.
Signal Select. Selects the GPIO signal to be configured in the Bank selected via bit 5 setting (i.e., Bank 0 or Bank 1). See
Table 3-2 on page 81 for GPIO ball muxing options. GPIOs without an associated ball number are not available externally.
Bank 0
000000 = GPIO0 (EBGA: H1 / TEPBGA: D11)
000001 = GPIO1 (EBGA: H2, AL12 / TEPBGA: D10, N30) 010001 = GPIO17 (EBGA: J4 / TEPBGA: A10)
000010 = GPIO2
000011 = GPIO3
000100 = GPIO4
000101 = GPIO5
000110 = GPIO6 (EBGA: AH3 / TEPBGA: D28)
000111 = GPIO7 (EBGA: AH4 / TEPBGA: C30)
001000 = GPIO8 (EBGA: AJ2 / TEPBGA: C31)
001001 = GPIO9 (EBGA: AG4 / TEPBGA: C28)
001010 = GPIO10 (EBGA: AJ1 / TEPBGA: B29)
001011 = GPIO11 (EBGA: H30 / TEPBGA: AJ8)
001100 = GPIO12 (EBGA: AJ12 / TEPBGA: N29)
001101 = GPIO13 (EBGA: AL11 / TEPBGA: M29)
001110 = GPIO14 (EBGA: F1 / TEPBGA: D9)
001111 = GPIO15 (EBGA: G3 / TEPBGA: A8)
Bank 1
100000 = GPIO32 (EBGA: AJ11 / TEPBGA: M28)
100001 = GPIO33 (EBGA: AL10 / TEPBGA: L31)
100010 = GPIO34 (EBGA: AK10 / TEPBGA: L30)
100011 = GPIO35 (EBGA: AJ10 / TEPBGA: L29)
100100 = GPIO36 (EBGA: AL9 / TEPBGA: L28)
100101 = GPIO37 (EBGA: AK9 / TEPBGA: K31)
100110 = GPIO38 (EBGA: AJ9 / TEPBGA: K28)
100111 = GPIO39 (EBGA: AL8 / TEPBGA: J31)
101000 = GPIO40 (EBGA: A21 / TEPBGA: Y3)
101001 = GPIO41 (EBGA: C19 / TEPBGA: W4)
101010 = GPIO42
101011 = GPIO43
101100 = GPIO44
101101 = GPIO45
101110 = GPIO46
101111 = GPIO47
Note:
Reserved. Must be set to 0.
PME Debounce Enable. Enables/disables IRQ debounce (debounce period = 16 ms).
0: Disable.
1: Enable. (Default).
See the note in the description of this register for more information about the default value of this bit.
PME Polarity. Selects the polarity of the signal that issues a PME from the selected GPIO signal (falling/low or rising/high).
0: Falling edge or low level input. (Default)
1: Rising edge or high level input.
See the note in the description of this register for more information about the default value of this bit.
Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)
GPIO63 can be used to generate the PWRBTN# input signal. See PWRBTN# signal description in Section 2.4.15
"Power Management Interface Signals" on page 74.
(Continued)
GPIO Signal Configuration Access Register (R/W)
GPIO Signal Configuration Select Register (R/W)
233
010000 = GPIO16 (EBGA: AL15 / TEPBGA: V31)
010010 = GPIO18 (EBGA: A28 / TEPBGA: AG1)
010011 = GPIO19 (EBGA: H4 / TEPBGA: C9)
010100 = GPIO20 (EBGA: H3, AJ13 / TEPBGA: A9, N31)
010101 = GPIO21
010110 = GPIO22
010111 = GPIO23
011000 = GPIO24
011001 = GPIO25
011010 = GPIO26
011011 = GPIO27
011100 = GPIO28
011101 = GPIO29
011110 = GPIO30
011111 = GPIO31
110000 = GPIO48
110001 = GPIO49
110010 = GPIO50
110011 = GPIO51
110100 = GPIO52
110101 = GPIO53
110110 = GPIO54
110111 = GPIO55
111000 = GPIO56
111001 = GPIO57
111010 = GPIO58
111011 = GPIO59
111100 = GPIO60
111101 = GPIO61
111110 = GPIO62
111111 = GPIO63 (Note)
Reset Value: 00000000h
Reset Value: 00000044h
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