SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 68

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Signal Definitions
2.4.9
Signal Name
IDE_RST#
IDE_ADDR2
IDE_ADDR1
IDE_ADDR0
IDE_DATA[15:0]
IDE_IOR0#
IDE_IOR1#
IDE_IOW0#
IDE_IOW1#
IDE_CS0#
IDE_CS1#
IDE_IORDY0
IDE_IORDY1
IDE_DREQ0
IDE_DREQ1
IDE_DACK0#
IDE_DACK1#
IDE Interface Signals
Table 2-3
on page
EBGA
AH3
AG4
AH4
A22
C17
C26
A26
See
C21
D24
A27
C16
A25
C24
C25
AJ1
AJ2
32.
(Continued)
Ball No.
TEPBGA
Table 2-5
on page
AD3
AD2
AD1
AC4
AD4
AA1
AE1
D28
C28
AF2
C31
C30
See
B29
U2
47.
Y4
P2
Type
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
Description
IDE Reset. This signal resets all the devices
that are attached to the IDE interface.
IDE Address Bits. These address bits are
used to access a register or data port in a
device on the IDE bus.
IDE Data Lines. IDE_DATA[15:0] transfers
data to/from the IDE devices.
IDE I/O Read Channels 0 and 1.
IDE_IOR0# is the read signal for Channel 0
and IDE_IOR1# is the read signal for Chan-
nel 1. Each signal is asserted at read
accesses to the corresponding IDE port
addresses.
IDE I/O Write Channels 0 and 1.
IDE_IOW0# is the write signal for Channel 0.
IDE_IOW1# is the write signal for Channel 1.
Each signal is asserted at write accesses to
corresponding IDE port addresses.
IDE Chip Selects 0 and 1. These signals are
used to select the command block registers
in an IDE device.
I/O Ready Channels 0 and 1. When deas-
serted, these signals extend the transfer
cycle of any host register access if the
required device is not ready to respond to the
data transfer request.
Note: If
DMA Request Channels 0 and 1. The
IDE_DREQ signals are used to request a
DMA transfer from the SC2200. The direction
of transfer is determined by the
IDE_IOR/IOW signals.
Note: If
DMA Acknowledge Channels 0 and 1. The
IDE_DACK# signals acknowledge the DREQ
request to initiate DMA transfers.
68
IDE_IORDY1 function(s) but not
used, then signal(s) should be tied
high.
IDE_DREQ1 function but not used,
tie IDE_DREQ0/IDE_DREQ1 low.
selected
selected
as
as
IDE_IORDY0
IDE_DREQ0/
or
BOUT2+SDTEST5#
The IDE interface is
muxed with the TFT
interface. See Table
2-7 on page 52 for
GPIO10+DSR2#+
GPIO9+DCD2#+
GPIO6+DTR2#/
GPIO8+CTS2#
GPIO7+RTS2#
+SDTEST5
+SDTEST0
SDTEST2
SDTEST1
TFTDCK
TFTD10
TFTD11
TFTDE
TFTD4
TFTD2
TFTD3
details.
TFTD9
TFTD5
TFTD8
TFTD0
Mux
Revision 3.0