SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 351

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Video Processor Module
Offset 404h-407h
Offset 408h-40Bh
Offset 40Ch-41Fh
Offset 420h-423h
Offset 424h-427h
Offset 428h-43Bh
Offset 43Ch-43Fh
31:24
31:21
31:16
31:0
21:9
20:0
15:0
1:0
Bit
23
22
8
7
6
5
4
3
2
1
0
Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
VID_SEL (Video Select). Selects the source of the video data.
00: GX1 module.
10: VIP block.
01: Reserved.
11: Reserved.
The GX1 module’s video clock must be active at all times, regardless of the source of video input.
Reserved.
Reserved. Must be set to 0.
0DD_TO (Odd Field Time Out). Indicates CGENTO0 (F4BAR0+Memory Offset 43Ch[15:0]) has expired. This bit can be
reset by writing 1 to it.
EVEN_TO (Even Field Time Out). Indicates CGENTO1 (F4BAR0+Memory Offset 43Ch[31:16]) has expired. This bit can
be reset by writing 1 to it.
Reserved.
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
GENLOCK_TOUT_EN (GenLock Timeout Enable).
0: Disable.
1: Enable timeout.
VIP_VSYNC_EDGE_SEL (VIP VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with VIP.
0: Rising edge.
1: Falling edge.
GX1_VSYNC_EDGE_SEL (GX1 VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with the GX1 module.
0: Rising edge.
1: Falling edge.
CT_GENLOCK_EN (Enable Continuous GenLock Function).
0: The continuous GenLock function is disabled.
1: Enable locking (i.e., synchronization) of the GX1 VSYNC with the VIP VSYNC on every VSYNC (i.e., continuous lock-
Note:
Note:
Reserved.
GENLOCK_DEL (GenLock Delay). Indicates the delay (in 27 MHz clocks) between the VIP VSYNC and the GX1 module’s
Display Controller VSYNC.
CGENTO1 (Even Field Continuous GenLock Timeout).
CGENTO0 (Odd Field Continuous GenLock Timeout).
ing).
If bit 0 (SG_GENLOCK_EN) = 1, it overrides the value of this bit.
Reserved. Set to 0.
(Continued)
Continuous GenLock Timeout Register (R/W)
Video Processor Test Mode Register (R/W)
GenLock Delay Register (R/W)
GenLock Register (R/W)
Reserved
Reserved
Reserved
351
Reset Value: 1FFF1FFFh
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
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