SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 201

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 09h-0Bh
Index 0Ch
Index 0Dh
Index 0Eh
Index 0Fh
This register indicates various information about the PCI Built-In Self-Test (BIST) mechanism.
Note:
Index 10h-13h
This register allows access to I/O mapped GPIO runtime and configuration Registers. Bits [5:0] are read only (000001), indicating a 64-
byte aligned I/O address space. Refer to Table 5-30 on page 231 for the GPIO register bit formats and reset values.
Index 14h-17h
This register allows access to I/O mapped LPC configuration registers. Bits [5:0] are read only (000001), indicating a 64-byte aligned I/O
address space. Refer to Table 5-31 on page 235 for the bit formats and reset values of the LPC registers.
Index 18h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
31:6
31:6
7:0
7:4
3:0
7:0
5:4
3:0
5:0
5:0
Bit
7
6
This mechanism is not supported in the Core Logic module in the SC2200.
Description
PCI Cache Line Size Register. This register sets the size of the PCI cache line, in increments of four bytes. For memory
write and invalidate cycles, the PCI cache line size must be set to 32 bytes (08h) and the Memory Write and Invalidate bit
(F0 Index 04h[4]) must be set to 1.
Reserved. Must be set to 0.
PCI Latency Timer Value. The PCI Latency Timer register prevents system lockup when a slave does not respond to a
cycle that the Core Logic module masters.
If the value is set to 00h (default), the timer is disabled.
If the timer is written with any other value, bits [3:0] become the four most significant bits in a timer that counts PCI clocks for
slave response.
The timer is reset on each valid data transfer. If the counter expires before the next assertion of TRDY# is received, the Core
Logic module stops the transaction with a master abort and asserts SERR#, if enabled to do so (via F0 Index 04h[8]).
PCI Header Type Register. This register defines the format of this header. This header has a format of type 0. (For more
information about this format, see the PCI Local Bus specification, revision 2.2.)
Additionally, bit 7 of this register defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).
BIST Capable. Indicates if the device can run a Built-In Self-Test (BIST).
0: The device has no BIST functionality.
1: The device can run a BIST.
Start BIST. Setting this bit to 1 starts up a BIST on the device. The device resets this bit when the BIST is completed. (Not
supported.)
Reserved.
BIST Completion Code. Upon completion of the BIST, the completion code is stored in these bits. A completion code of
0000 indicates that the BIST was successfully completed. Any other value indicates a BIST failure.
GPIO Base Address.
Address Range. (Read Only)
LPC Base Address.
Address Range. (Read Only)
(Continued)
Base Address Register 0 - F0BAR0 (R/W)
Base Address Register 1 - F0BAR1 (R/W)
PCI Cache Line Size Register (R/W)
PCI Latency Timer Register (R/W)
PCI Class Code Register (RO)
Subsystem Vendor ID (RO)
PCI BIST Register (RO)
PCI Header Type (RO)
Subsystem ID (RO)
Reserved
Reserved
201
Reset Value: 00000001h
Reset Value: 00000001h
Reset Value: 060100h
Reset Value: 100Bh
Reset Value: 0500h
Reset Value: 00h
Reset Value: 00h
Reset Value: 80h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
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