SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 17

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Architecture Overview
• LPC: See Section 2.4.8 "Low Pin Count (LPC) Bus Inter-
• Sub-ISA: See Section 2.4.7 "Sub-ISA Interface Signals"
• GPIO: See Section 2.4.16 "GPIO Interface Signals" on
• More detailed information about each of these interfaces
• Super/IO Block Interfaces: See Section 3.2 "Multi-
The Core Logic module interface to the GX1 module con-
sists of seven miscellaneous connections, the PCI bus
interface signals, plus the display controller connections.
Note that the PC/AT legacy signals NMI, WM_RST, and
A20M are all virtual functions executed in SMM (System
Management Mode) by the BIOS.
• PSERIAL is a one-way serial bus from the GX1 to the
• IRQ13 is an input from the processor indicating that a
• INTR is the level output from the integrated 8259A PICs
• SMI# is a level-sensitive interrupt to the GX1 that can be
• SUSP# and SUSPA# are handshake signals for imple-
• CPU_RST resets the CPU and is asserted for approxi-
• PCI bus interface signals.
face Signals" on page 67.
on page 66, Section 5.2.5 "Sub-ISA Bus Interface" on
page 156, and Section 3.2 "Multiplexing, Interrupt Selec-
tion, and Base Address Registers" on page 81
page 75.
is provided in Section 5.2 "Module Architecture" on page
151.
plexing, Interrupt Selection, and Base Address Regis-
ters" on page 81, Section 2.4.5 "ACCESS.bus Interface
Signals" on page 60, Section 2.4.13 "Fast Infrared (IR)
Port Interface Signals" on page 72, and Section 2.4.12
"Parallel Port Interface Signals" on page 71.
Core Logic module used to communicate power-
management states and VSYNC information for VGA
emulation.
floating point error was detected and that INTR should
be asserted.
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
configured to assert on a number of different system
events. After an SMI# assertion, SMM is entered and
program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
menting CPU Clock Stop and clock throttling.
mately 100 µs after the negation of POR#.
(Continued)
17
1.4
The SuperI/O (SIO) module is a member of National Semi-
conductor’s SuperI/O family of integrated PC peripherals. It
is a PC98 and ACPI compliant SIO that offers a single-cell
solution to the most commonly used ISA peripherals.
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
1.5
In addition to the four main modules (i.e., GX1, Core Logic,
Video Processor and SIO) that make up the SC2200, the
following blocks of logic have also been integrated into the
SC2200:
• Clock Generators as described in Section 3.5 "Clock
• Configuration Registers as described in Section 3.2
• A WATCHDOG timer as described in Section 3.3
• A High-Resolution timer as described in Section 3.4
1.5.1
This section provides a description of the reset flow of the
SC2200.
1.5.1.1
Power-On reset is triggered by assertion of the POR# sig-
nal. Upon power-on reset, the following things happen:
• Strap balls are sampled.
• PLL4, PLL5, and PLL6 are reset, disabling their output.
• Certain WATCHDOG and High-Resolution Timer
1.5.1.2
System reset causes signal PCIRST# to be issued, thus
triggering reset of all PCI and LPC agents. A system reset
is triggered by any of the following events:
• Power-on, as indicated by POR# signal assertion.
• A WATCHDOG reset event (see Section 3.3.2
• Software initiated system reset.
Generators and PLLs" on page 93.
"Multiplexing, Interrupt Selection, and Base Address
Registers" on page 81.
"WATCHDOG" on page 88.
"High-Resolution Timer" on page 91.
When the POR# signal is negated, the clocks lock and
then each PLL outputs its clock. PLL6 is the last clock
generator to output a clock. See Section 3.5 "Clock
Generators and PLLs" on page 93.
register bits are cleared.
"WATCHDOG Registers" on page 89).
SUPERI/O MODULE
CLOCK, TIMERS, AND RESET LOGIC
Reset Logic
Power-On Reset
System Reset
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