SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 334

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Video Processor Module
6.3
The register space for accessing and configuring the Video
Processor is located in the Core Logic Chipset Register
Space (F0-F5). The Chipset Register Space is accessed
via the PCI interface using the PCI Type One Configuration
Mechanism (see Section 5.3.1 "PCI Configuration Space
and Access Methods" on page 184).
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Bh
3Ch
3Dh
3Eh-FFh
F4 Index
REGISTER DESCRIPTIONS
Width
(Bits)
32
32
16
16
16
16
24
32
16
16
---
8
8
8
8
8
--
--
8
8
Table 6-3. F4: PCI Header Registers for Video Processor Support Summary
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
---
--
--
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F4BAR0). Sets the base address for the
memory-mapped Video Configuration Registers within the Video
Processor. Refer to Table 6-7 on page 339 for programming infor-
mation regarding the register offsets accessed through this regis-
ter.
Base Address Register 1 (F4BAR1). Reserved.
Base Address Register 2 (F4BAR2). Sets the base address for the
memory-mapped VIP (Video Interface Port) Registers (summa-
rized in Table 6-8 on page 352).
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
Interrupt Line Register
Interrupt Pin Register
Reserved
(Continued)
334
6.3.1
The tables in this subsection summarize the registers of
the Video Processor. Included in the tables are the regis-
ter’s reset values and page references where the bit for-
mats are found.
Register Summary
00000000h
00000000h
00000000h
030000h
100Bh
0504h
0000h
0280h
100Bh
0504h
Reset
Value
01h
00h
00h
00h
00h
00h
00h
00h
03h
00h
(Table 6-6)
Reference
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Revision 3.0