SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 222

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

www.national.com
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 9Ch-9Dh
Index 9Eh-9Fh
Index A0h-A1h
Index A2h-A3h
Index A4h-A5h
15:0
15:0
15:0
15:0
15:0
Bit
Description
Parallel / Serial Idle Timer Count. This idle timer is used to determine when the parallel and serial ports are not in use so
that the ports can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port
is not considered here.
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[2] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[2].
Keyboard / Mouse Idle Timer Count. This idle timer determines when the keyboard and mouse are not in use so that the
LCD screen can be blanked. The 16-bit value programmed in this register represents the period of inactivity for these ports
after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access
occurs to either the keyboard or mouse I/O address spaces (including the mouse serial port address space when a mouse
is enabled on a serial port.)
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[3] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[3].
User Defined Device 1 (UDEF1) Idle Timer Count. This idle timer determines when the device configured as User Defined
Device 1 (UDEF1) is not in use so that it can be power managed. The 16-bit value programmed in this register represents
the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with
the count value whenever an access occurs to memory or I/O address space configured in the F0 Index C0h (Base Address
register) and F0 Index CCh (Control register).
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[4] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[4].
User Defined Device 2 (UDEF2) Idle Timer Count. This idle timer determines when the device configured as UDEF2 is not
in use so that it can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to memory or I/O address space configured in the F0 Index C4h (Base Address register) and F0 Index
CDh (Control register).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[5] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[5].
User Defined Device 3 (UDEF3) Idle Timer Count. This idle timer determines when the device configured as UDEF3 is not
in use so that it can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index C8h) and
UDEF3 Control Register (F0 Index CEh).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[6] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[6].
(Continued)
User Defined Device 1 Idle Timer Count Register (R/W)
User Defined Device 2 Idle Timer Count Register (R/W)
User Defined Device 3 Idle Timer Count Register (R/W)
Keyboard / Mouse Idle Timer Count Register (R/W)
Parallel / Serial Idle Timer Count Register (R/W)
222
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0000h
Revision 3.0