IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 105

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Figure 5–23. 256-Bit Avalon-ST tx_sd_data Cycle Definition for 3-DWord Header TLP with QWord Aligned Address
Figure 5–24. Location of Headers and Data for Avalon-ST 256-Bit Interface
December 2010 Altera Corporation
4DW header,
Aligned data
tx_st_data[191:128]
tx_st_data[255:192]
tx_st_data[127:64]
255
tx_st_data[63:0]
0
tx_st_emp[1:0]
D3
D2
D1
D0
H3
H2
H1
H0
tx_st_sop
Figure 5–23
with aligned and unaligned data.
Figure 5–24
This layout of data applies to both the TX and RX buses.
clk
D9
D8
D7
D6
D5
D4
4DW header,
Unaligned data
illustrates the layout of header and data for a 3-DWord header for 256-bit
shows the location of headers and data for the 256-bit Avalon-ST packets.
255
0
D2
D1
D0
H3
H2
H1
H0
XXXXXXXXX XXXXXXXX
D9
D8
D7
D6
D5
D4
D3
XXXXXXXX Header 2
Header 1 Header 0
XXXXXXXX Data 0
Aligned Data
01
3DW header,
Aligned data
255
0
XXXXXXXXX XXXXXXXX
XXXXXXXXX XXXXXXXX
D3
D2
D1
D0
H2
H1
H0
Header 1 Header 0
Data 0 Header 2
Unaligned Data
D9
D8
D7
D6
D5
D4
10
3DW header,
Unaligned data
PCI Express Compiler User Guide
255
0
D4
D3
D2
D0
H2
H1
H0
D1
D9
D8
D7
D6
D5
5–21