IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 345

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Avalon-MM Interface
Table C–4. Performance and Resource Utilization, Avalon-ST Interface - Stratix III Family
Table C–5. Performance and Resource Utilization, Avalon-ST Interface - Stratix IV Family
Avalon-MM Interface
December 2010 Altera Corporation
Note to
(1) C4 device used.
(2) C3 device used.
×1
×1
×1/ ×4
×1
×1
×4
×4
×1/ ×4
(1)
(2)
×1
×1
×4
×4
Table
Stratix III Family
Stratix IV Family
C–4:
Clock (MHz)
Parameters
Internal
Clock (MHz)
Parameters
62.5
62.5
125
125
125
125
Internal
Table C–4
Stratix III (EP3SL200F1152C2) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 10.1.
Table C–5
Stratix IV GX (EP3SGX290FH29C2X) devices for a maximum payload of 256 bytes
with different parameters, using the Quartus II software, version 10.1.
the soft IP implementation for various parameters when using the SOPC Builder
design flow to create a design with an Avalon-MM interface and the following
parameter settings:
■
This section tabulates the typical expected performance and resource utilization for
125
125
125
125
On the Buffer Setup page, for ×1, ×4 configurations:
■
■
Maximum payload size set to 256 Bytes unless specified otherwise
Desired performance for received requests and Desired performance for
completions set to Medium unless specified otherwise
Channels
shows the typical expected performance and resource utilization of
shows the typical expected performance and resource utilization of
Virtual
1
2
1
2
1
2
Channels
Virtual
1
2
1
2
Combinational
Combinational
ALUTs
5300
6800
5500
6800
7000
8500
ALUTs
5500
6900
7100
8500
Registers
Logic
4500
5900
4800
6000
5300
6500
Registers
Logic
4100
5200
5100
6200
Size
Size
M9K Memory
Blocks
M9K Memory
11
15
5
9
5
8
Blocks
14
10
18
PCI Express Compiler User Guide
9
M144K Memory
Blocks
M144K
0
0
0
1
0
0
0
0
1
0
C–3