IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 291

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 16: SOPC Builder Design Example
Complete the Connections in SOPC Builder
December 2010 Altera Corporation
3. To connect cal_clk, complete following these steps:
4. To specify the interrupt number for DMA interrupt sender, irq, type a 0 in the IRQ
5. In the Base column, enter the base addresses in
Table 16–7. Base Addresses for Slave Ports
SOPC Builder generates informational messages indicating the actual PCI BAR
settings.
For this example BAR1:0 is sized to 4 KBytes or 12 bits; PCI Express requests that
match this BAR, are able to access the Avalon addresses from 0x80000000–
0x80000FFF. BAR2 is sized to 32 KBytes or 15 bits; matching PCI Express requests are
able to access Avalon addresses from 0x8000000–0x80007FFF. The DMA
control_port_slave is accessible at offsets 0x1000 through 0x103F from the
programmed BAR2 base address. The pci_express_compiler_0
Control_Register_Access slave port is accessible at offsets 0x4000–0x7FFF from the
programmed BAR2 base address. Refer to
Translation” on page 4–19
For Avalon-MM accesses directed to the pci_express_compiler_0 TX_interface port,
Avalon-MM address bits 19-0 are passed through to the PCI Express address
unchanged because a 1 MByte or 20–bit address page size was selected. Bit 20 is used
to select which one of the 2 address translation table entries is used to provide the
upper bits of the PCI Express address. Avalon address bits [31:21] are used to select
the TX_interface slave port. Refer to section
Translation” on page 4–20
pci_express_compiler_0 Control_Register_Access
pci_express_compiler_0 TX_Interface
dma_0 control_port_slave
onchip_memory2_0 s1
a. Click in the Clock column next to the cal_blk_clk port. A list of available
b. Click cal_clk from the list of available clocks to connect the calibration clock
1
column next to the irq port.
system.
clock signals appears.
(cal_blk_clk) of the pci_express_compiler.
All components using transceivers must have their cal_blk_clk connected
to the same clock source.
Port
for additional information on this address mapping.
for additional information on this address mapping.
“PCI Express-to-Avalon-MM Address
“Avalon-MM-to-PCI Express Address
0x80004000
0x00000000
0x80001000
0x80000000
Table 16–7
for all the slaves in your
PCI Express Compiler User Guide
Address
16–7