IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 165

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Reset and Clocks
Reset in Stratix V Devices
December 2010 Altera Corporation
Upon exit from any reset, all port registers and state machines must be set to their
initialization values with the exception of sticky registers as defined Sections 7.4 and
7.6 of the
sources, both external and internal to implement these resets. These signals are
described in
To meet 100 ms PCIe configuration time, a reset controller implemented as a hard
macro handles the initial reset of the PMA, PCS, and PCI Express IP core. Once the
PCI Express link has been established, a soft reset controller handles warm and hot
resets. The <variant>_plus.v or .vhd IP cores include soft reset logic. You can use the
<variant>.v or .vhd if you want to specify your own soft reset sequence.
provides a high-level block diagram for the reset logic.
Figure 7–4. Stratix V Reset Block Diagram
Reset Signal Domains, Hard IP and ×1 and ×4 Soft IP Implementations
This section discusses the domain of each of the reset signal in the <variant>.v or .vhd
IP core.
The hard IP implementation (×1, ×4, and ×8) or the soft IP implementation (×1 and
×4) have the following three reset inputs:
Reset Synchronization
<variant> _rs_hip.v
or .vhd
Circuitry from Design
Example for Stratix V
PCI Express Base
“Reset and Link Training Signals” on page
Specification. The PCI Express IP core has several reset
<variant>_plus .v or .vhd
pld_clrpmapcship
pld_clk_in_use
pld_clk_ready
reset_status
pld_clrhip
perst_n
<variant> .v or .vhd
<variant> _serdes.v or .vhd
PCIe Hard IP Core
5–24.
Reset Logic
PHY IP
PCI Express Compiler User Guide
Figure 7–4
7–5