IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 87

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Figure 5–2. Signals in the Hard IP Implementation Endpoint with Avalon-ST Interface
Notes to
(1) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. The reconfig_fromgxb is a single wire for Stratix II GX and
(2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> = 2. For
December 2010 Altera Corporation
Arria GX. For Stratix IV GX, <n> = 16 for ×1 and ×4 IP cores and <n> = 33 the ×8 IP core.
Stratix IV GX, <n> = 3.
Channel <n> )
Reset &
Training
Figure
Link
(Path to
Tx Port
Virtual
5–2:
Reconfiguration
<variant> _plus
(optional)
<variant>
ECC Error
Clocks
Component
Block
Completion
Interface
Component
Avalon-ST
Avalon-ST
Interrupt
Power
Mnmt
Specific
Specific
avs_pcie_reconfig_address[7:0]
avs_pcie_reconfig_byteenable[1:0]
avs_pcie_reconfig_chipselect
avs_pcie_reconfig_write
avs_pcie_reconfig_writedata[15:0]
avs_pcie_reconfig_waitrequest
avs_pcie_reconfig_read
avs_pcie_reconfig_readdata[15:0]
avs_pcie_reconfig_readdatavalid
avs_pcie_reconfig_clk
avs_pcie_reconfig_rstn
rx_st_ready <n>
rx_st_valid <n>
rx_st_data <n> [63:0], [127:0]
rx_st_sop <n>
rx_st_eop <n>
rx_st_empty <n>
rx_st_err <n>
rx_st_mask <n>
rx_st_bardec <n> [7:0]
rx_st_be <n> [7:0], [15:0]
tx_st_ready <n>
tx_st_valid <n>
tx_st_data <n> [63:0], [127:0]
tx_st_sop <n>
tx_st_eop <n>
tx_st_empty <n>
tx_st_err <n>
tx_fifo_full <n>
tx_fifo_empty <n>
tx_fifo_rdptr <n> [3:0]
tx_fifo_wrptr <n> [3:0]
tx_cred <n> [35:0]
nph_alloc_1cred_vc0
npd_alloc_1cred_vc0
npd_cred_vio_vc0
nph_cred_vio_vc0
refclk
pld_clk
core_clk_out
pcie_rstn
local_rstn
suc_spd_neg
dl_ltssm[4:0]
npor
srst
crst
l2_exit
hotrst_exit
dlup_exit
reset_status
rc_pll_locked
derr_cor_ext_rcv[1:0]
derr_rpl
derr_cor_ext_rpl
r2c_err0
r2c_err1
app_msi_req
app_msi_ack
app_msi_tc[2:0]
app_msi_num[4:0]
pex_msi_num[4:0]
app_int_sts
app_int_ack
pme_to_cr
pme_to_sr
pm_event
pm_data
pm_auxpwr
cpl_err[6:0]
cpl_pending <n>
Signals in the PCI Express Hard IP Core
reset_reconfig_altgxb_reconfig
busy_reconfig_altgxb_reconfig
(1)
reconfig_fromgxb[ <n> :0]
(2)
reconfig_togxb[ <n> :0]
powerdown0_ext[1:0]
rx_st_fifo_empty <n>
rxstatus0_ext[2:0]
rx_st_fifo_full <n>
gxb_powerdown
rxdata0_ext[7:0]
txdata0_ext[7:0]
tx_pipedeemph
tl_cfg_sts[52:0]
txdetectrx0_ext
phystatus0_ext
rxelecidle0_ext
tl_cfg_add[3:0]
txelecidle0_ext
tl_cfg_ctl[31:0]
rxpolarity0_ext
tx_pipemargin
test_out[63:0]
lmi_dout[31:0]
lmi_addr[11:0]
tl_cfg_sts_wr
txcompl0_ext
lane_act[3:0]
rxdatak0_ext
txdatak0_ext
tl_cfg_ctl_wr
reconfig_clk
lmi_din[31:0]
test_in[39:0]
rxvalid0_ext
cal_blk_clk
clk250_out
clk500_out
pipe_mode
hpg_ctrler
pipe_txclk
pipe_rstn
lmi_wren
lmi_rden
rate_ext
fixedclk
tx_out0
tx_out1
tx_out2
tx_out3
tx_out4
tx_out5
tx_out6
tx_out7
pclk_in
lmi_ack
rx_in0
rx_in1
rx_in2
rx_in3
rx_in4
rx_in5
rx_in6
rx_in7
PCI Express Compiler User Guide
<variant> _plus.v or .vhd )
internal
Serial
8-bit
PIPE
Test
Interface
PHY
IF to
PIPE
Config
for
LMI
Simulation
These signals are
Clocks -
Only
Transceiver
internal for
Control
Simulation
Interface
Only (4)
PIPE
5–3