IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 319

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Table B–6. Standard TX Descriptor Phase Signals (Part 2 of 2)
Table B–7. Standard TX Data Phase Signals (Part 1 of 2)
December 2010 Altera Corporation
tx_desc<n>[127:0]
(cont.)
tx_ack<n>
Note to
(1) For all signals, <n> is the virtual channel number which can be 0 or 1.
tx_dfr<n>
tx_dv<n>
tx_ws<n>
Table
Signal
Signal
B–6:
(1)
Table B–7
I/O
O
I
I
I/O
O
I
Transmit data phase framing. This signal is asserted on the same clock cycle as tx_req to
request a data phase (assuming a data phase is needed). This signal must be kept asserted
until the clock cycle preceding the last data phase.
Transmit data valid. This signal is asserted by the user application interface to signify that
the tx_data[63:0] signal is valid. This signal must be asserted on the clock cycle
following assertion of tx_dfr until the last data phase of transmission. The IP core
accepts data only when this signal is asserted and as long as tx_ws is not asserted.
The application interface can rely on the fact that the first data phase never occurs before a
descriptor phase is acknowledged (through assertion of tx_ack). However, the first data
phase can coincide with assertion of tx_ack if the transaction layer packet header is only 3
DWORDS.
Transmit wait states. The IP core uses this signal to insert wait states that prevent data
loss. This signal might be used in the following circumstances:
■
■
If the IP core is not ready to acknowledge a descriptor phase (through assertion of tx_ack
on the following cycle), it will automatically assert tx_ws to throttle transmission. When
tx_dv is not asserted, tx_ws should be ignored.
describes the standard TX data phase signals.
Bit 126 of the descriptor indicates the type of transaction layer packet in transit:
■
■
The following list provides a few examples of bit fields on this bus:
■
■
■
Transmit acknowledge. This signal is asserted for one clock cycle when the IP core
acknowledges the descriptor phase requested by the application through the tx_req
signal. On the following clock cycle, a new descriptor can be requested for transmission
through the tx_req signal (kept asserted) and the tx_desc.
To give a DLLP transmission priority.
To give a high-priority virtual channel or the retry buffer transmission priority when the
link is initialized with fewer lanes than are permitted by the link.
tx_desc[126] when 0: transaction layer packet without data
tx_desc[126] when 1: transaction layer packet with data
tx_desc[105:96]: length[9:0]
tx_desc[126:125]: fmt[1:0]
tx_desc[126:120]: type[4:0]
Description
Description
PCI Express Compiler User Guide
B–13