IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 99

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–4. 64-, 128-, or 256-Bit Avalon-ST TX Datapath (Part 3 of 5)
December 2010 Altera Corporation
tx_fifo_rdptr<n>[3:0]
tx_fifo_wrptr[3:0]
tx_cred<n>
nph_alloc_1cred_vc0
npd_alloc_1cred_vc0
npd_cred_vio_vc0
nph_cred_vio_vc0
Signal
(3) (4) (5) (6)
(5) (6)
(5) (6)
Component Specific Signals for Arria II GX, HardCopy IV, and Stratix IV
(5) (6)
(5) (6)
4
4
36
1
1
1
1
Width Dir
O
O
O
O
O
O
O
component
specific
component
specific
component
specific
component
specific
component
specific
component
specific
component
specific
Avalon-ST
Type
This is the read pointer for the adaptor TX FIFO. Does not
apply to Stratix V devices.
This is the write pointer for the adaptor TX FIFO. Does not
apply to Stratix V devices.
This vector contains the available header and data credits
for each type of TLP (completion, non-posted, and
posted). Each data credit is 4 dwords or 16 bytes as per
the PCI Express Base Specification. Use of the signal is
optional.
If more TX credits are available than the tx_cred bus can
display, tx_cred shows the maximum number given the
number of bits available for that particular TLP type.
tx_cred is a saturating bus and for a given TLP type, it
does not change until enough credits have been
consumed to fall within the range tx_cred can display.
Refer to
For information about how to use the tx_cred signal
optimize flow control refer to
Used in conjunction with the optional tx_cred<n>
signal. When 1, indicates that the non-posted header
credit limit was initialized to only 1 credit. This signal is
asserted after FC Initialization and remains asserted until
the link is reinitialized.
Used in conjunction with the optional tx_cred<n>
signal. When 1, indicates that the non-posted data credit
limit was initialized to only 1 credit. This signal is
asserted after FC Initialization and remains asserted until
the link is reinitialized.
Used in conjunction with the optional tx_cred<n>
signal. When 1, means that the non-posted data credit
field is no longer valid so that more credits were
consumed than the tx_cred signal advertised. Once a
violation is detected, this signal remains high until the IP
core is reset.
Used in conjunction with the optional tx_cred<n>
signal. When 1, means that the non-posted header credit
field is no longer valid. This indicates that more credits
were consumed than the tx_cred signal advertised.
Once a violation is detected, this signal remains high until
the IP core is reset.
Figure 5–15
for the layout of fields in this signal.
Description
“Tx Datapath” on page
PCI Express Compiler User Guide
4–5.
5–15