IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 242

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–14
Table 15–4. Design Example BAR Map
Table 15–5. Chaining DMA Control Register Definitions
Table 15–6. Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read Control Register
PCI Express Compiler User Guide
32-bit BAR4
32-bit BAR5
64-bit BAR5:4
Expansion ROM BAR
I/O Space BAR (any)
Addr
Note to
(1) Refer to
(2) This is the endpoint byte address offset from BAR2 or BAR3.
16
17
18
[24:20]
0x1C DMA Rd Cntl DW3
0x10 DMA Rd Cntl DW0
0x14 DMA Rd Cntl DW1
0x18 DMA Rd Cntl DW2
(2)
0xC
0x0
0x4
0x8
Bit
Table
DMA Wr Cntl DW0
DMA Wr Cntl DW1
DMA Wr Cntl DW2
DMA Wr Cntl DW3
Chaining DMA Control and Status Registers
Reserved
MSI_ENA
EPLAST_ENA
MSI Number
Figure 15–3 on page 15–8
Register Name
15–5:
Field
The software application programs the chaining DMA control register located in the
endpoint application.
dwords for the DMA write and four dwords for the DMA read. The DMA control
registers are read/write.
Table 15–6
registers.
Maps to 32 KByte target memory block. Use the rc_slave module to bypass the chaining DMA.
Not implemented by design example; behavior is unpredictable.
Not implemented by design example; behavior is unpredictable.
3124
for a block diagram of the chaining DMA design example that shows these registers.
describes the control fields of the of the DMA read and DMA write control
Base Address of the Write Descriptor Table (BDT) in the RC Memory–Upper DWORD
Base Address of the Write Descriptor Table (BDT) in the RC Memory–Lower DWORD
Base Address of the Read Descriptor Table (BDT) in the RC Memory–Lower DWORD
Base Address of the Read Descriptor Table (BDT) in the RC Memory–Upper DWORD
Control Field (refer to
Control Field (refer to
Reserved
Reserved
Enables interrupts of all descriptors. When 1, the endpoint DMA module issues an
interrupt using MSI to the RC when each descriptor is completed. Your software
application or BFM driver can use this interrupt to monitor the DMA transfer status.
Enables the endpoint DMA module to write the number of each descriptor back to
the EPLAST field in the descriptor table.
table.
When your RC reads the MSI capabilities of the endpoint, these register bits map to
the PCI Express back-end MSI signals app_msi_num [4:0]. If there is more than
one MSI, the default mapping if all the MSIs are available, is:
■
■
MSI 0 = Read
MSI 1 = Write
Table 15–5
2316
(Note 1)
Table
Table
describes the control registers which consists of four
15–6)
15–6)
Description
150
RCLAST–Idx of last descriptor to process
RCLAST–Idx of the last descriptor to process
Number of descriptors in descriptor table
Number of descriptors in descriptor table
—
Table 15–10
Chapter 15: Testbench and Design Example
describes the descriptor
December 2010 Altera Corporation
Chaining DMA Design Example