IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 17

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: Datasheet
General Description
December 2010 Altera Corporation
Device Programming Modes with PCI Express Initialization
The Stratix V architecture introduces a new option for sequencing the processes that
configure the FPGA and initialize the PCI Express link. In prior devices, a monolithic
Program Object File (.pof) programmed the I/O ring and FPGA fabric before the PCIe
link training and enumeration began. In Stratix V, the .pof file is divided into two
parts. The IO bitstream contains the data to program the I/O ring and PCI Express IP
core. The core bitstream contains the data to program the FPGA fabric.
In Stratix V devices, the I/O ring and PCI Express link are programmed first, allowing
the PCI Express link to reach the L0 state and begin operation independently, before
the rest of the core is
used to program the rest of the device. Programming the FPGA fabric using the PCIe
link is called Configuration via PCI Express (CvPCIe).
that implement CvPCIe.
Figure 1–2. CvPCIe in Stratix V Devices
CvPCIe has the following advantages:
■
■
■
■
■
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It provides a simpler software model for configuration. A smart host can use the
PCIe protocol and the application topology to initialize and update the FPGA
fabric.
It enables dynamic core updates without requiring a system power down.
It improves security for the proprietary core bitstream.
It reduces system costs by reducing the size of the flash device to store the .pof.
It facilitates hardware acceleration.
It may reduce system size because a single CvPCIe link can be used to configure
multiple FPGAs.
Host CPU
programmed.
Configuration via
PCIe Port
USB Port
PCI Express
(CvPCIe)
Download cable
After the PCI Express link is established, it can be
IP Core
PCIe
Quad Flash
Config Cntl
Serial or
Stratix V Device
Block
Figure 1–3
Device Configuration
Active Serial or
Active Quad
PCI Express Compiler User Guide
shows the blocks
1–7