IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 32

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–6
View Generated Files
PCI Express Compiler User Guide
Table 2–5. Power Management Parameters (Part 2 of 2)
14. Click Next (or the EDA page) to display the simulation setup page.
15. On the EDA tab, turn on Generate simulation model to generate an IP functional
16. On the Summary tab, select the files you want to generate. A gray checkmark
17. Click Finish to generate the IP core, testbench, and supporting files.
18. Click Yes when you are prompted to add the Quartus II IP File (.qip) to the project.
Figure 2–4
the PCI Express IP core. The directories includes the following files:
■
■
Endpoint L0s acceptable latency
Common clock
Separate clock
Electrical idle exit (EIE) before FTS
Enable L1 ASPM
Endpoint L1 acceptable latency
L1 Exit Latency Common clock
L1 Exit Latency Separate clock
simulation model for the IP core. An IP functional simulation model is a
cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software.
c
indicates a file that is automatically generated. All other files are optional.
1
The .qip is a file generated by the parameter editor or SOPC Builder that contains
all of the necessary assignments and information required to process the core or
system in the Quartus II compiler. Generally, a single .qip file is generated for each
IP core.
The PCI Express IP core design files, stored in <working_dir>.
The chaining DMA design example file, stored in the
<working_dir>\top_examples\chaining_dma sub-directory. This design example
tests your generated PCIe variation. For detailed information about this design
example, refer to
Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a non-functional
design.
A report file, <variation name>.html, in your project directory lists each file
generated and provides a description of its contents.
illustrates the directory structure created for this design after you generate
Parameter
Chapter 15, Testbench and Design
L1s Active State Power Management (ASPM)
Number of fast training sequences (N_FTS)
< 64 ns
Gen2: 255
Gen2: 255
4
Off
< 1 µs
> 64 µs
> 64 µs
Example.
December 2010 Altera Corporation
Value
Chapter 2: Getting Started
View Generated Files