IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 145

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Space Register Content
Table 6–1. Common Configuration Space Header (Part 1 of 2)
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
0x000:0x03C
0x000:0x03C
0x040:0x04C
0x050:0x05C
0x068:0x070
0x070:0x074
0x078:0x07C
0x080:0x0B8
0x080:0x0B8
0x0B8:0x0FC
0x094:0x0FF
0x100:0x16C
0x170:0x17C
0x180:0x1FC
0x200:0x23C
0x240:0x27C
0x280:0x2BC
Byte Offset
f
1
PCI Type 0 configuration space header (refer to
PCI Type 1 configuration space header (refer to
Reserved
MSI capability structure, version 1.0a and 1.1 (refer to
MSI–X capability structure, version 2.0 (refer to
Reserved
Power management capability structure (refer to
PCI Express capability structure (refer to
PCI Express capability structure (refer to
Reserved
Root port
Virtual channel capability structure (refer to
Reserved
Virtual channel arbitration table
Port VC0 arbitration table (Reserved)
Port VC1 arbitration table (Reserved)
Port VC2 arbitration table (Reserved)
This section describes registers that you can access the PCI Express configuration
space and the Avalon-MM bridge control registers. It includes the following sections:
■
■
■
Table 6–1
provide more details.
For comprehensive information about these registers, refer to Chapter 7 of the
Express Base Specification Revision 1.0a, 1.1 or 2.0
on the System Setting page of the MegaWizard interface.
To facilitate finding additional information about these PCI Express registers, the
following tables provide the name of the corresponding section in the
Specification Revision 2.0.
Configuration Space Register Content
PCI Express Avalon-MM Bridge Control Register Content
Comprehensive Correspondence between Config Space Registers and PCIe Spec
Rev 2.0
31:24
shows the common configuration space header. The following tables
23:16
Table 6–7
Table 6–8
Table 6–9
Table 6–2
Table 6–3
Table 6–5
Table 6–6
for details.)
for details.)
for details.)
Table 6–4
6. Register Descriptions
depending on the version you specify
for details.)
for details.)
for details.)
for details.)
15:8
for details.)
PCI Express Compiler User Guide
PCI Express Base
7:0
PCI