IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 108

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–24
Table 5–7. Reset and Link Training Signals (Part 1 of 3)
PCI Express Compiler User Guide
pcie_rstn
local_rstn
suc_spd_neg
dl_ltssm[4:0]
dl_ltssm[4:0]
(continued)
Signal
Reset and Link Training Signals
Table 5–7
interface or descriptor/data interface.
I/O
O
O
O
I
I
pcie_rstn directly resets all sticky PCI Express IP core configuration registers. Sticky
registers are those registers that fail to reset in L2 low power mode or upon a fundamental
reset. This is an asynchronous reset. This signal is not used in Stratix V devices.
reset_n is the system-wide reset which resets all PCI Express IP core circuitry not affected by
pcie_rstn. This is an asynchronous reset.This signal is not used in Stratix V devices.
Indicates successful speed negotiation to Gen2 when asserted. This signal is not used in
Stratix V devices.
LTSSM state: The LTSSM state machine encoding defines the following states:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
01110: recovery.idle
10000: disable
10011: loopback.exit
10100: hot.reset
00000: detect.quiet
00001: detect.active
00010: polling.active
00011: polling.compliance
00100: polling.configuration
00101: polling.speed
00110: config.linkwidthstart
00111: config.linkaccept
01000: config.lanenumaccept
01001: config.lanenumwait
01010: config.complete
01011: config.idle
01100: recovery.rcvlock
01101: recovery.rcvconfig
01111: L0
10001: loopback.entry
10010: loopback.active
10110: L1.entry
10111: L1.idle
11000: L2.idle
11001: L2.transmit.wake
Both <variant>_plus.v or .vhd and <variant>.v or .vhd
describes the reset signals available in configurations using the Avalon-ST
<variant>_plus.v or .vhd
Description
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface