IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 233

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Root Port Testbench
December 2010 Altera Corporation
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Table 15–2. Gen2 ×8 IP core Endpoint Parameterization
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■
The testbench has routines that perform the following tasks:
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■
Parameter
Lanes
Port Type
Max rate
BAR Type
Device ID
Vendor ID
Tags supported
MSI messages requested
Error Reporting
Maximum payload size
Number of virtual channels
altpcietb_bfm_ep_example_chaining_pipen1b—This is the endpoint PCI
Express model. The EP BFM consists of a Gen2 ×8 IP core endpoint connected to
the chaining DMA design example described in the section
Design Example” on page
Gen2 ×8 IP core endpoint.
altpcietb_pipe_phy—There are eight instances of this module, one per lane. These
modules connect the PIPE MAC layer interfaces of the root port and the endpoint.
The module mimics the behavior of the PIPE PHY layer to both MAC interfaces.
altpcietb_bfm_driver_rp—This module drives transactions to the root port BFM.
This is the module that you modify to vary the transactions sent to the example
endpoint design or your own design. For more information about this module, see
“Test Driver Module” on page
Generates the reference clock for the endpoint at the required frequency.
Provides a PCI Express reset at start up.
Value
8
Native Endpoint
Gen2
BAR1:0—64–bit Prefetchable Memory, 256 MBytes–28 bits
Bar 2:—32–Bit Non-Prefetchable, 256 KBytes–18 bits
0xABCD
0x1172
32
4
Implement ECRC check,
Implement ECRC generations
Implement ECRC generate and forward
128 bytes
1
15–6.
15–18.
Table 15–2
shows the parameterization of the
PCI Express Compiler User Guide
“Chaining DMA
15–5