IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 43

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

System Settings
Table 3–1. System Settings Parameters (Part 1 of 4)
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
PCIe Core Type
PHY type
Parameter
This chapter describes the PCI Express Compiler IP core parameters, which you can
set on the Parameter Settings tab.
The first page of the Parameter Settings tab contains the parameters for the overall
system settings.
PCI Express hard IP
PCI Express soft IP
Custom
Stratix II GX
Stratix IV GX
Stratix V GX
Stratix V GX CVP
Cyclone IV GX
Value
Table 3–1
PCIe System Parameters
The hard IP implementation uses embedded dedicated logic to
implement the PCI Express protocol stack, including the physical layer,
data link layer, and transaction layer.
The soft IP implementation uses optimized PLD logic to implement the
PCI Express protocol stack, including physical layer, data link layer, and
transaction layer.
Allows all types of external PHY interfaces (except serial). The number of
lanes can be ×1 or ×4. This option is only available for the soft IP
implementation.
Serial interface where Stratix II GX uses the Stratix II GX device family's
built-in transceiver. Selecting this PHY allows only a serial PHY interface
with the lane configuration set to Gen1 ×1, ×4, or ×8.
Serial interface where Stratix IV GX uses the Stratix IV GX device
family's built-in transceiver to support PCI Express Gen1 and Gen2 ×1,
×4, and ×8. For designs that may target HardCopy IV GX, the
HardCopy IV GX setting must be used even when initially compiling for
Stratix IV GX devices. This procedure ensures that you only apply
HardCopy IV GX compatible settings in the Stratix IV GX
implementation.
Serial interface where Stratix V GX uses the Stratix V GX device family's
built-in transceiver to support PCI Express Gen1 and Gen2 ×1, ×4, and
×8.
If you select this option, the Quartus II software places the PCI Express
IP core in the location required for CvPCIe.
Serial interface where Cyclone IV GX uses the Cyclone IV GX device
family’s built-in transceiver. Selecting this PHY allows only a serial PHY
interface with the lane configuration set to Gen1 ×1, ×2, or ×4.
describes these settings.
Description
3. Parameter Settings
PCI Express Compiler User Guide