IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 222

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

14–6
Figure 14–5. 8-bit SDR Mode - 250 MHz
PCI Express Compiler User Guide
8-bit SDR with a Source Synchronous TXClk
External connection
in user logic
clk125_out
clk125_in
rxdata
refclk (pclk) 250 MHz
■
An edge detect circuit detects the relationships between the 125 MHz clock and the
250 MHz rising edge to properly sequence the 16-bit data into the 8-bit output
register.
Figure 14–6
synchronous TXClk. It is included in the file <variation name>.v or
<variation name>.vhd and includes a PLL. refclk (pclk from the external PHY) drives
the PLL inclock. The PLL has the following outputs:
■
■
■
txdata
An optional 62.5 MHz TLP Slow clock is provided for ×1 implementations.
A 125 MHz output derived from the 250 MHz refclk. This 125 MHz PLL output is
used as the clk125_in for the IP core.
A 250 MHz early output that is skewed early in relation to the refclk the 250 MHz
early clock PLL output clocks an 8-bit SDR transmit data output register.
An optional 62.5 MHz TLP Slow clock is provided for ×1 implementations.
illustrates the implementation of the 16-bit SDR mode with a source
Mode 4
A
D
PLL
& Sync
Detect
Edge
ENB
Q
Q
1
4
ENB
Q
Q
1
4
A
D
A
D
A
D
clk250_early
ENB
ENB
Q
Q
1
4
ENB
Q
Q
Q
Q
1
4
1
4
A
D
A
D
A
D
ENB
ENB
Q
Q
Q
Q
1
4
1
4
rxdata_h
rxdata_l
txdata_h
txdata_l
clk125_in
tlp_clk
refclk
MegaCore Function
December 2010 Altera Corporation
PCI Express
Chapter 14: External PHYs
External PHY Support