IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 154

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–10
Table 6–17. Avalon-MM-to-PCI Express Address Translation Table
Table 6–18. PCI Express Avalon-MM Bridge Address Space Bit Encodings
PCI Express Compiler User Guide
0x1000
0x1004
0x1008
0x100C
Note to
(1) These table entries are repeated for each address specified in the Number of address pages parameter
00
01
10
11
(Bits 1:0)
of address pages is set to the maximum of 512, 0x1FF8 contains A2P_ADDR_MAP_LO511 and 0x1FFC contains A2P_ADDR_MAP_HI511.
Address
Value
Table
PCI Express to Avalon-MM Interrupt Status and Enable Registers
6–17:
[1:0]
[31:2]
[31:0]
[1:0]
[31:2]
[31:0]
Memory Space, 32-bit PCI Express address. 32-bit header is generated.
Address bits 63:32 of the translation table entries are ignored.
Memory space, 64-bit PCI Express address. 64-bit address header is generated.
Reserved
Reserved
Bits
Each entry in the PCI Express address translation table
regardless of the value in the current PCI Express address width parameter. Therefore,
register addresses are always the same width, regardless of PCI Express address
width.
The format of the address space field (A2P_ADDR_SPACEn) of the address
translation table entries is shown in
The registers in this section contain status of various signals in the PCI Express
Avalon-MM bridge logic and allow Avalon interrupts to be asserted when enabled. A
processor local to the system interconnect fabric that processes the Avalon-MM
interrupts can access these registers. These registers must not be accessed by the PCI
Express Avalon-MM bridge master ports; however, there is nothing in the hardware
that prevents this.
A2P_ADDR_SPACE0
A2P_ADDR_MAP_LO0
A2P_ADDR_MAP_HI0
A2P_ADDR_SPACE1
A2P_ADDR_MAP_LO1
A2P_ADDR_MAP_HI1
Name
Access
RW
RW
RW
RW
RW
RW
Table
Indication
Address space indication for entry 0. Refer to
for the definition of these bits.
Lower bits of Avalon-MM-to-PCI Express address map
entry 0.
Upper bits of Avalon-MM-to-PCI Express address map
entry 0.
Address space indication for entry 1. Refer to
for the definition of these bits.
Lower bits of Avalon-MM-to-PCI Express address map
entry 1.
This entry is only implemented if number of table entries
is greater than 1.
Upper bits of Avalon-MM-to-PCI Express address map
entry 1.
This entry is only implemented if the number of table
entries is greater than 1.
6–18.
PCI Express Avalon-MM Bridge Control Register Content
(Table
Description
(Table 3–6 on page
Address Range: 0x1000-0x1FFF
December 2010 Altera Corporation
Chapter 6: Register Descriptions
6–17) is 8 bytes wide,
3–14). If Number
Table 6–18
Table 6–18