IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 219

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 14: External PHYs
External PHY Support
Figure 14–2. 16-bit SDR Mode with a 125 MHz Source Synchronous Transmit Clock
December 2010 Altera Corporation
8-bit DDR Mode
clk125_in
clk125_out
■
■
This is the only external PHY mode that does not require a PLL. However, if the slow
tlp_clk feature is used with this PIPE interface mode, then a PLL is required to create
the slow tlp_clk. In the case of the slow tlp_clk, the circuit is similar to the one
shown previously in
The implementation of the 8-bit DDR mode shown in
file <variation name>.v or <variation name>.vhd and includes a PLL. The PLL inclock is
driven by refclk (pclk from the external PHY) and has the following outputs:
■
■
External connection in user logic
refclk clocks the transmit data register (txdata) directly
refclk also clocks a DDR register that is used to create a center aligned TXClk
A zero delay copy of the 125 MHz refclk. The zero delay PLL output is used as
the clk125_in for the core and clocks a double data rate register for the incoming
receive data.
A 250 MHz early output. This is multiplied from the 125 MHz refclk is early in
relation to the refclk. Use the 250 MHz early clock PLL output to clock an 8-bit
SDR transmit data output register. A 250 MHz single data rate register is used for
the 125 MHz DDR output because this allows the use of the SDR output registers
in the Cyclone II I/O block. The early clock is required to meet the required clock
to out times for the common refclk for the PHY. You may need to adjust the phase
shift for your specific PHY and board delays. To alter the phase shift, copy the PLL
refclk (pclk)
rxdata
txdata
txclk (~refclk)
Figure
A
D
Q
Q
Q
Q
DDIO
1
1
ENB
4
ENB
4
ENB
Q
Q
A
D
A
D
14–1, the 16-bit SDR, but with TXClk output added.
1
4
Figure 14–3
refclk
clk125_in
tlp_clk
MegaCore Function
PCI Express
clk125_out
PCI Express Compiler User Guide
is included in the
14–3