IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 34

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–8
PCI Express Compiler User Guide
f
Figure 2–5
the PCI Express IP core connects to a basic root port bus functional model (BFM) and
an application layer high-performance DMA engine. These two modules, when
combined with the PCI Express IP core, comprise the complete example design. The
test stimulus is contained in altpcietb_bfm_driver_chaining.v. The script to run the
tests is runtb.do. For a detailed explanation of this example design, refer to
Chapter 15, Testbench and Design
Figure 2–5. Testbench for the Chaining DMA Design Example
The design files used in this design example are the same files that are used for the
PCI Express High-Performance Reference
files on the
product page includes design files for various devices. The example in this document
uses the Stratix IV GX files. You also must also download altpcie_demo.zip which
includes a software driver that the example design uses.
The Stratix IV .zip file includes files for Gen1 and Gen2 ×1, ×4, and ×8 variants. The
example in this document demonstrates the Gen2 ×8 variant. After you download
and unzip this .zip file, you can copy the files for this variant to your project directory,
<working_dir>. The files for the example in this document are included in the
hip_s4gx_gen2x8_128 directory. The Quartus II project file, top.qsf, is contained in
<working_dir>. You can use this project file as a reference.
illustrates the top-level modules of this design. As this figure illustrates,
PCI Express High-Performance Reference Design
Endpoint Example
Endpoint Application
Layer Example
(Optional)
Slave
RC
Traffic Control/Virtual Channel Mapping
Root Port BFM
Request/Completion Routing
Example.
x8 Root Port Model
Root Port Driver
PCI Express
(32 KBytes)
Endpoint
Memory
IP Core
Write
DMA
Design. You can download the required
PCI Express Link
DMA
Read
December 2010 Altera Corporation
product page. This
Chapter 2: Getting Started
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