IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 358

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Info–6
PCI Express Compiler User Guide
October 2005
April 2006
April 2006
December
December
December
May 2008
May 2007
May 2007
October
2006
2006
2006
Date
Version
2.1.0
2.1.0
2.0.0
rev 2
8.0
7.2
7.1
7.0
7.1
7.0
6.1
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Added information describing PCI Express hard IP IP core.
Moved sections describing signals to separate chapter.
Corrected description of
Corrected
system no longer requires an interrupt.
Improved description of
names and added descriptions of additional modules.
Removed descriptions of Type 0 and Type 1 Configuration Read/Write requests because they
are not used in the PCI Express endpoint.
Added missing signal descriptions for Avalon-ST interface.
Completed connections for
Expanded definition of Quartus II .qip file.
Added instructions for connecting the calibration clock of the PCI Express Compiler.
Updated discussion of clocking for external PHY.
Removed simple DMA design example.
Added support for Avalon-ST interface in the MegaWizard Plug-In Manager flow.
Added single-clock mode in SOPC Builder flow.
Re-organized document to put introductory information about the core first and streamline
the design examples and moved detailed design example to a separate chapter.
Corrected text describing reset for ×1, ×4 and ×8 IP cores.
Corrected Timing Diagram: Transaction with a Data Payload.
Added support for Arria GX device family.
Added SOPC Builder support for ×1 and ×4.
Added Incremental Compile Module (ICM).
Maintenance release; updated version numbers.
Minor format changes throughout user guide.
Added support for Arria GX device family.
Added SOPC Builder support for ×1 and ×4.
Added Incremental Compile Module (ICM).
Added support for Cyclone III device family.
Added support Stratix III device family.
Updated version and performance information.
Rearranged content.
Updated performance information.
Added ×8 support.
Added device support for Stratix
Updated performance information.
Figure 16–3 on page 16–8
Chapter 15, Testbench and Design
cpl_err
npor
®
in
II GX and Cyclone
signals.
Figure 5–26 on page
Changes Made
showing connections for SOPC Builder system. This
®
II.
5–26.
Example. Corrected module
December 2010 Altera Corporation
Additional Information
Revision History
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