IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 168

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–8
Figure 7–6. Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix IV GX, Stratix V GX ×1, ×4, or ×8 100 MHz Reference
Clock
Note to
(1) Different device families require different frequency ranges for the calibration and reconfiguration clocks. To determine the frequency range for
PCI Express Compiler User Guide
your device, refer to one of the following device handbooks:
in Volume 2 of the Cyclone IV Device Handbook,
Guide
Figure
for Stratix V devices.
7–6:
Clock Source
Clock Source
Clock Source
Clock Source
Calibration
100-MHz
Reconfig
Fixed
Figure 7–6
The IP core contains a clock domain crossing (CDC) synchronizer at the interface
between the PHY/MAC and the DLL layers which allows the data link and
transaction layers to run at frequencies independent of the PHY/MAC and provides
more flexibility for the user clock interface to the IP core. Depending on system
requirements, this additional flexibility can be used to enhance performance by
running at a higher frequency for latency optimization or at a lower frequency to save
power.
illustrates this clocking configuration.
<variant>.v or .vhd
refclk
Transceiver Architecture
<variant>_serdes.v or .vhd
rx_cruclk
pll_inclk
cal_blk_clk
reconfig_clk
fixedclk
(PCIe MegaCore Function)
<variant>_core.v or .vhd
(ALTGX or ALT2GX
Transceiver Architecture
Megafunction)
tx_clk_out
in Volume 2 of the Stratix IV Device Handbook, or
in Volume II of the Arria II Device Handbook,
125 MHz - x1 or x4
core_clk_out
250 MHz - x8
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
Application Clock
Altera PHY IP User
Transceivers
Clocks