IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 347

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Avalon-MM Interface
December 2010 Altera Corporation
Stratix II GX Devices
Stratix III Family
Table C–7. Performance and Resource Utilization, Avalon-MM Interface - Cyclone III Family
Table C–8
Stratix II and Stratix II GX (EP2SGX130GF1508C3) devices for a maximum payload of
256 bytes with different parameters, using the Quartus II software, version 10.1.
Table C–8. Performance and Resource Utilization, Avalon-MM Interface - Stratix II GX Devices
Table C–9
Stratix III (EPSL200F1152C2) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 10.1.
Table C–9. Performance and Resource Utilization, Avalon-MM Interface - Stratix III Family
Note to
(1) Maximum payload of 128 bytes. C8 device used.
Note to
(1) C4 device used.
×1
×1/ ×4
×1/ ×4
×1/ ×4
×1
×4
×4
Table
Table
×1
×4
(1)
Parameters
shows the typical expected performance and resource utilization of
shows the typical expected performance and resource utilization of
Parameters
C–7:
C–4:
Parameters
Clock (MHz)
Clock (MHz)
Internal Clock
Internal
Internal
125
125
62.5
125
125
(MHz)
125
Combinational
Combinational
ALUTs
Logic Elements
6600
8100
ALUTs
6900
7100
8700
12700
Dedicated
Registers
5000
5800
Dedicated
Registers
Dedicated
Registers
Size
Size
5200
5500
6500
5400
Size
PCI Express Compiler User Guide
M512
Memory Blocks
2
7
M9K Memory
M9K Memory
Blocks
Blocks
17
22
17
37
M4K
33
32
C–5