IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 21

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: Datasheet
General Description
December 2010 Altera Corporation
External PHY Support
Debug Features
f
1
Table 1–7. Operation in Devices with HSSI Transceivers (Part 2 of 2)
The device names and part numbers for Altera FPGAs that include internal
transceivers always include the letters GX or GT. If you select a device that does not
include an internal transceiver, you can use the PIPE interface to connect to an
external PHY.
You can customize the payload size, buffer sizes, and configuration space (base
address registers support and other registers). Additionally, the PCI Express Compiler
supports end-to-end cyclic redundancy code (ECRC) and advanced error reporting
for ×1, ×2, ×4, and ×8 configurations.
Altera PCI Express IP cores support a wide range of PHYs, including the TI XIO1100
PHY in 8-bit DDR/SDR mode or 16-bit SDR mode; NXP PX1011A for 8-bit SDR mode,
a serial PHY, and a range of custom PHYs using 8-bit/16-bit SDR with or without
source synchronous transmit clock modes and 8-bit DDR with or without source
synchronous transmit clock modes. You can constrain TX I/Os by turning on the Fast
Output Enable Register option in the parameter editor, or by editing this setting in
the Quartus II Settings File (.qsf). This constraint ensures fastest t
The PCI Express IP cores also include debug features that allow observation and
control of the IP cores for faster debugging of system-level problems.
For more information about debugging refer to
Stratix IV GX hard IP–Gen1
Stratix IV GX hard IP–Gen 2
Stratix IV soft IP–Gen1
Cyclone IV GX hard IP–Gen1
Arria II GX–Gen1 Hard IP Implementation
Arria II GX–Gen1 Soft IP Implementation
Arria II GZ–Gen1 Hard IP Implementation
Arria II GZ–Gen2 Hard IP Implementation
Arria GX
Stratix II GX
Notes to
(1) Refer to
(2) Not available in -4 speed grade. Requires -2 or -3 speed grade.
(3) Gen2 ×8 is only available in the -2 and -I3 speed grades.
Table
Table 1–2 on page 1–3
1–7:
Device Family
Table 3–1 on page 3–1
for a list of features available in the different implementations.
lists the available external PHY types.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
×1
(2)
Chapter 17,
Yes
Debugging.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
×4
PCI Express Compiler User Guide
(Note 1)
(2)
CO
timing.
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
×8
(3)
1–11