IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 208

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

13–2
Table 13–1. Dynamically Reconfigurable Registers in the Hard IP Implementation (Part 1 of 7)
PCI Express Compiler User Guide
0x00
0x01-0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
Address
Bits
15:0 Vendor ID.
15:0 Device ID.
15:8
15:0 Class code[23:8].
15:0 Subsystem vendor ID.
15:0 Subsystem device ID.
15:8
7:0
3:1 Low Priority VC (LPVC).
7:4
2:0
0
0 Advanced Error Reporting.
Table 13–1
reconfiguration block interface.
When 0, PCIe reconfig mode is enabled. When 1, PCIe
reconfig mode is disabled and the original read only
register values set in the programming file used to
configure the device are restored.
Reserved.
Revision ID.
Class code[7:0].
Reserved.
Max payload size supported. The following are the defined
encodings:
VC arbitration capabilities.
Reject Snoop Transaction.d
000: 128 bytes max payload size.
001: 256 bytes max payload size.
010: 512 bytes max payload size.
011: 1024 bytes max payload size.
100: 2048 bytes max payload size.
101: 4096 bytes max payload size.
110: Reserved.
111: Reserved.
lists all of the registers that you can update using the PCI Express
Description
Chapter 13: Reconfiguration and Offset Cancellation
b’00000000
b’00001
Default
0x1172
0x0001
0x1172
0x0001
Value
b’000
b’010
0x01
b’1
b’0
—
—
—
—
December 2010 Altera Corporation
Table 6–2 on page
Table 6–3 on page 6–3
Table 6–2 on page
Table 6–3 on page 6–3
Table 6–2 on page
Table 6–3 on page 6–3
Table 6–2 on page
Table 6–3 on page 6–3
Table 6–2 on page 6–2
Table 6–2 on page 6–2
Table 6–2 on page 6–2
Table 6–9 on page 6–5
Port VC Cap 1
Table 6–9 on page 6–5
VC Resource Capability
register
Table 6–8 on page
Device Capability
register
Additional Information
Dynamic Reconfiguration
—
6–2,
6–2,
6–2,
6–2,
6–5,