IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 326

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–20
Figure B–16. TX Transfer with Wait State Inserted for a Single DWORD Write
Figure B–17. TX Signal Activity When IP core Has Fewer than Maximum Potential Lanes Waveform
PCI Express Compiler User Guide
Descriptor
Signals
Data
Signals
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_data[31:0]
Figure B–16
wait state signal.
Transaction Layer Inserts Wait States because of Four Dword Header
In this example, the application transmits a 64-bit memory write transaction. Address
bit 2 is set to 1. Refer to
data phases because the IP core implements a small buffer to give maximum
performance during transmission of back-to-back transaction layer packets.
tx_ack
tx_req
tx_ws
tx_err
tx_ack
tx_dfr
tx_dv
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
clk
clk
1
1
shows how the transaction layer extends the a data phase by asserting the
2
MEMWR32
2
3
DW 1
DW 0
Figure
4
DW 3
DW 2
3
B–18. No wait states are inserted during the first two
5
MEMWR32
6
4
DW 5
DW 4
7
8
DW0
5
9
December 2010 Altera Corporation
10
6
DW 7
DW 6
11
Descriptor/Data Interface
12
7
13
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