IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 163

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Reset and Clocks
Reset Soft IP Implementation
Figure 7–2. Reset Signals in the Hard IP Variant
Reset Soft IP Implementation
December 2010 Altera Corporation
<variant>.v or .vhd
125 or 250 MHz
pld_clk
If you choose to implement your own reset circuitry, you must design logic to replace
the Transceiver Reset module shown in
Figure 7–2
<variant>.v or .vhd reset logic.
Figure 7–3
implementation. To use this variant, you must design the logic to implement reset and
calibration. For designs that use the internal ALTGX transceiver, the PIPE interface is
transparent. You can use the reset sequence provided for the hard IP implementation
in the <variant>_rs_hip.v or .vhd IP core as a reference in designing your own circuit.
In addition, to understand the domain of each reset signal, refer to
Domains, Hard IP and ×1 and ×4 Soft IP Implementations” on page
<variant>.v or .vhd
<variant>_core.v
PCI Express
Hard IP
or .vhd
provides a somewhat more detailed view of the reset signals in the
dl_ltssm[4:0]
shows the global reset signals for ×1 and ×4 endpoints in the soft IP
Hip_txclk 125 or 250 MHz
npor
altpcie_rs_serdes.v
Transceiver Reset
rx_analogreset
rx_digitalreset
tx_digitalreset
or .vhd
busy_altgxb_reconfig
Figure
7–1.
125 MHz
fixedclk
rx_freqlocked
pll_locked
rx_pll_locked
Transceiver PHY IP Core
<variant>_serdes.v
or .vhd
cal_blk_clk
50 MHz
PCI Express Compiler User Guide
“Reset Signal
100 MHz
7–5.
Refclk
7–3