IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 310

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–4
Table B–2. RX Descriptor Phase Signals (Part 1 of 2)
PCI Express Compiler User Guide
rx_req<n>
rx_desc<n>[135:0]
rx_ack<n>
rx_abort<n>
rx_retry<n>
Signal
(1)
Table B–2
I/O
O
O
I
I
I
describes the standard RX descriptor phase signals.
Receive request. This signal is asserted by the IP core to request a packet transfer to the
application interface. It is asserted when the first 2 DWORDS of a transaction layer
packet header are valid. This signal is asserted for a minimum of 2 clock cycles;
rx_abort, rx_retry, and rx_ack cannot be asserted at the same time as this signal.
The complete descriptor is valid on the second clock cycle that this signal is asserted.
Receive descriptor bus. Bits [125:0] have the same meaning as a standard transaction
layer packet header as defined by the
or
header occupies bits [119:112], and so on, with byte 15 in bits [7:0]. Refer to
Appendix A, Transaction Layer Packet (TLP) Header Formats
For bits [135:128] (descriptor and BAR decoding), refer to
transactions received by an endpoint do not have any bits asserted and must be routed
to the master block in the application layer.
rx_desc[127:64] begins transmission on the same clock cycle that rx_req is
asserted, allowing precoding and arbitration to begin as quickly as possible. The other
bits of rx_desc are not valid until the following clock cycle as shown in the following
figure.
Bit 126 of the descriptor indicates the type of transaction layer packet in transit:
■
■
Receive acknowledge. This signal is asserted for 1 clock cycle when the application
interface acknowledges the descriptor phase and starts the data phase, if any. The
rx_req signal is deasserted on the following clock cycle and the rx_desc is ready for
the next transmission. rx_ack is independent of rx_dv and rx_data. It cannot be
used to backpressure rx_data. You can use rx_ws to insert wait states.
Receive abort. This signal is asserted by the application interface if the application
cannot accept the requested descriptor. In this case, the descriptor is removed from the
receive buffer space, flow control credits are updated, and, if necessary, the application
layer generates a completion transaction with unsupported request (UR) status on the
transmit side.
Receive retry. The application interface asserts this signal if it is not able to accept a
non-posted request. In this case, the application layer must assert rx_mask<n> along
with rx_retry<n> so that only posted and completion transactions are presented on
the receive interface for the duration of rx_mask<n>.
2.0. Byte 0 of the header occupies bits [127:120] of the rx_desc bus, byte 1 of the
rx_desc[126]when set to 0: transaction layer packet without data
rx_desc[126] when set to 1: transaction layer packet with data
rx_desc[135:128]
rx_desc[127:64]
rx_desc[63:0]
rx_ack
rx_req
PCI Express Base Specification Revision 1.0a, 1.1
Description
clk
1
2
valid
3
valid
valid
4
December 2010 Altera Corporation
Table
for the header formats.
B–3. Completion
Descriptor/Data Interface
Chapter :