IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 265

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–27.
Table 15–28. ebfm_cfgwr_imm_nowt Procedure (Part 1 of 2)
December 2010 Altera Corporation
Location
Syntax
Arguments
Location
Syntax
ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr, regb_len, imm_data)
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num, imm_regb_ad, regb_ln, imm_data,
compl_status
bus_num
dev_num
fnc_num
regb_ad
regb_ln
imm_data
compl_status
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_cfgwr_imm_wait Procedure
The ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified
configuration register. This procedure waits until the write completion has been
returned.
ebfm_cfgwr_imm_nowt Procedure
The ebfm_cfgwr_imm_nowt procedure writes up to four bytes of data to the specified
configuration register. This procedure returns as soon as the VC interface module
accepts the transaction, allowing other writes to be issued in the interim. Use this
procedure only when successful completion status is expected.
PCI Express bus number of the target device.
PCI Express device number of the target device.
Function number in the target device to be accessed.
Byte-specific address of the register to be written.
Length, in bytes, of the data written. Maximum length is four bytes. The regb_ln and
the regb_ad arguments cannot cross a DWORD boundary.
Data to be written.
In VHDL, this argument is a std_logic_vector(31 downto 0).
In Verilog HDL, this argument is reg [31:0].
In both languages, the bits written depend on the length:
In VHDL. this argument is a std_logic_vector(2 downto 0) and is set by the
procedure on return.
In Verilog HDL, this argument is reg [2:0].
In both languages, this argument is the completion status as specified in the PCI
Express specification:
Length
Compl_StatusDefinition
000SC— Successful completion
001UR— Unsupported Request
010CRS — Configuration Request Retry Status
100CA — Completer Abort
4
3
2
1
Bits Written
31 downto 0
23 downto 0
5 downto 0
7 downto 0
ebfm_cfgwr_imm_wait Procedure
PCI Express Compiler User Guide
15–37